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| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
|---|---|---|---|---|---|---|---|---|
| N/A | N/A | Macro | N/A | Macro | N/A | Macro | Macro | Macro |
LD4, LD8, and LD16 have, respectively, 4, 8, and 16 transparent data latches with a common gate enable (G). The data output (Q) of the latch reflects the data (D) input while the gate enable (G) input is High. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains Low.
The latch is asynchronously cleared, output Low, when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
Refer to the “LD” section for information on single transparent data latches.
| Inputs | Outputs | |
|---|---|---|
| G | D | Q |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| 0 | X | No Chg |
 | D | d |
| d = state of input one setup time prior to High-to-Low gate transition | ||
Figure 7.6 LD8 Implementation XC4000X, XC9000, SpartanXL, Spartan2, Virtex