Libraries GuideChapter 7: Design Elements (LD to NOR16)
LDC
Transparent Data Latch with Asynchronous Clear
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
N/A
| N/A
| Macro
| Macro
| N/A
| N/A
| Macro
| Primitive
| Primitive
|
LDC is a transparent data latch with asynchronous clear. When the asynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D) input while the gate enable (G) input is High and CLR is Low. The data on the D input during the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged as long as G remains low.
The latch is asynchronously cleared with Low output when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR (XC5200) and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
CLR
| G
| D
| Q
|
|---|
1
| X
| X
| 0
|
0
| 1
| 0
| 0
|
0
| 1
| 1
| 1
|
0
| 0
| X
| No Chg
|
0
| 
| D
| d
|
d = state of input one setup time prior to High-to-Low gate transition
|
Figure 7.7 LDC Implementation XC4000X, SpartanXL