OFDEX, 4, 8, 16

D Flip-Flops with Active-High Enable Output Buffers and Clock Enable

OFDEX, OFDEX4, OFDEX8, and OFDEX16 are single or multiple D flip-flops whose outputs are enabled by tristate buffers. The flip-flop data outputs (Q) are connected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs. These flip-flops and buffers are contained in input/output blocks (IOB). The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. When the active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the O outputs. When E is Low, outputs are high impedance (Z state or Off). When CE is Low and E is High, the outputs do not change.

The flip-flops are asynchronously cleared with Low outputs when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.

Inputs				Outputs
CE	E	D	C	O
X	0	X	X	Z, not off
1	1	1		1
1	1	0		0
0	1	X	X	No Chg

Figure 8.20 OFDEX Implementation XC4000E, XC4000X, Spartan, SpartanXL

Figure 8.21 OFDEX8 Implementation XC4000E, XC4000X, Spartan, SpartanXL