|
|
|
|
|
| Element | XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
|---|---|---|---|---|---|---|---|---|---|
| OFDTX | N/A | Primitive | Primitive | N/A | N/A | Primitive | Primitive | N/A | N/A |
| OFDTX4, OFDTX8, OFDTX16 | N/A | Macro | Macro | N/A | N/A | Macro | Macro | N/A | N/A |
OFDTX, OFDTX4, OFDTX8, and OFDTX16 are single or multiple D flip-flops whose outputs are enabled by a tristate buffers. The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of the OBUFTs (O) are connected to OPADs or IOPADs. These flip-flops and buffers are located in input/output blocks (IOB) for XC4000E. The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on the flip-flop outputs (Q) appears on the O outputs. When T is High, outputs are high impedance (Off). When CE is Low and T is Low, the outputs do not change.
The flip-flops are asynchronously cleared with Low output when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.
| Inputs | Outputs | |||
|---|---|---|---|---|
| CE | T | D | C | Q |
| X | 1 | X | X | Z |
| 1 | 0 | D |  | d |
| 0 | 0 | X | X | No Chg |
| d = state of referenced input one setup time prior to active clock transition | ||||
Figure 8.37 OFDTX8 Implementation XC4000E, XC4000X, Spartan, SpartanXL