OFDTX_1

D Flip-Flop with Active-Low 3-State Output Buffer, Inverted Clock, and Clock Enable

OFDTX_1 and its output buffer are located in an input/output block (IOB). The flip-flop data output (Q) is connected to the input of an output buffer (OBUFT). The OBUFT output is connected to an OPAD or an IOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition. When the active-Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the O output. When T is High, the output is high impedance (Off). When CE is High and T is Low, the outputs do not change.

The flip-flop is asynchronously cleared with Low output when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP symbol.

Inputs				Outputs
CE	T	D	C	Q
X	1	X	X	Z
1	0	1		0
1	0	0		0
0	0	X	X	No Chg

Figure 8.38 OFDTX_1 Implementation XC4000E, XC4000X, Spartan, SpartanXL