Libraries GuideChapter 8: Design Elements (OAND2 to OXOR2)
OFD_1
Output D Flip-Flop with Inverted Clock
XC3000
| XC4000E
| XC4000X
| XC5200
| XC9000
| Spartan
| SpartanXL
| Spartan2
| Virtex
|
|---|
Macro
| Macro
| Macro
| Macro
| N/A
| Macro
| Macro
| Macro
| Macro
|
OFD_1 is located in an input/output block (IOB) except for XC5200. The output (Q) of the D flip-flop is connected to an OPAD or an IOPAD. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition and appears on the Q output.
The flip-flop is asynchronously cleared, output Low, when power is applied. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
Inputs
| Outputs
|
|---|
D
| C
| Q
|
|---|
D
| 
| d
|
d = state of referenced input one setup time prior to active clock transition
|
Figure 8.10 OFD_1 Implementation XC3000, XC4000E, XC4000X, Spartan, SpartanXL