OFDE, 4, 8, 16

D Flip-Flops with Active-High Enable Output Buffers

OFDE, OFDE4, OFDE8, and OFDE16 are single or multiple D flip-flops whose outputs are enabled by tristate buffers. The flip-flop data outputs (Q) are connected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs. These flip-flops and buffers are contained in input/output blocks (IOB) for XC3000 and XC4000. The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. When the active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the O outputs. When E is Low, outputs are high impedance (Z state or Off).

The flip-flops are asynchronously cleared with Low outputs when power is applied. For CPLDs, the power-on condition can be simulated by applying a High-level pulse on the PRLD global net. FPGAs simulate power-on when global reset (GR) or global set/reset (GSR) is active. GR for XC3000 is active-Low. GR for XC5200 and GSR (XC4000, Spartans, Virtex) default to active-High but can be inverted by adding an inverter in front of the GR/GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.

Inputs			Outputs
E	D	C	O
0	X	X	Z, not off
1	1		1
1	0		0

Figure 8.12 OFDE Implementation XC3000, XC4000E, XC4000X, Spartan, SpartanXL

Figure 8.13 OFDE Implementation XC5200, Spartan2, Virtex

Figure 8.14 OFDE Implementation XC9000

Figure 8.15 OFDE8 Implementation XC3000, XC4000E, XC4000X, XC5200, XC9000, Spartan, SpartanXL, Spartan2, Virtex