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Synthesis and Simulation Design Guide

Appendix B

Report Files

This appendix includes report files from various synthesis vendors. To reduce the size of this appendix, some of the files are truncated (indicated by a series of dots) where information is repeated. This appendix contains the following sections.

Synplicity

Synplicity® report files include the following.

Note: The report file in this section is for a design compiled with the VHDL compiler. A report file for a design compiled with the Verilog compiler is essentially the same.

Content-Type: text/plain; charset="us-ascii"

Content-Disposition: attachment; filename="atm_chip1_ed.log"



$ Start of Compile

#Mon Jan 12 07:59:16 1998



Synplify VHDL Compiler, version 3.0b, built Dec 17 1997

Copyright (C) 1994-1997, Synplicity Inc.  All Rights Reserved



VHDL syntax check successful!



Compiler output is up to date.  No re-compile necessary



Synthesizing work.acc_chip.schematic

@N:"e:\customer\atm\lcl_int1.vhd":73:6:73:7|Trying to extract state machine for register wr_state_o

Extracted state machine for register wr_state_o

State machine has 4 reachable states with original encodings of:

   11

   10

   01

   00

@N:"e:\customer\atm\lcl_int1.vhd":73:6:73:7|Trying to extract state machine for register rd_state_o

Extracted state machine for register rd_state_o

State machine has 5 reachable states with original encodings of:

   00001

   00010

   00100

   01000

   10000

Post processing for work.acc_chip.schematic

@END

Process took 0.371 seconds realtime, 0.371 seconds cputime

Synplify Xilinx Technology Mapper, version 3.0b, built Dec 21 1997

Copyright (C) 1994-1997, Synplicity Inc.  All Rights Reserved

Setting fanout limit to 100

@N:"e:\customer\atm\token1.vhd":103:8:103:9|Found counter in view:work.TOKEN(vhdl_rtl) inst token_cntr[5:0]

@N:"e:\customer\atm\rx_agen1.vhd":61:6:61:7|Found counter in view:work.RX_ADD_GEN(vhdl_rtl) inst rx_20_add[18:0]

@N:"e:\customer\atm\rx_agen1.vhd":61:6:61:7|Found counter in view:work.RX_ADD_GEN(vhdl_rtl) inst rx_10_add[18:0]

@N:"e:\customer\atm\slw_clk1.vhd":21:10:21:11|Found counter in view:work.SLOW_CLOCKS(vhdl_rtl) inst slow_counter[16:0]

@N:"e:\customer\atm\mngmnt1.vhd":998:4:998:5|Found counter in view:work.MNGMNT(vhdl_rtl) inst tx_frame_cntr[11:0]

@N:"e:\customer\atm\mngmnt1.vhd":931:4:931:5|Found counter in view:work.MNGMNT(vhdl_rtl) inst rx_frame_cntr[11:0]



Clock Buffers:

  Inserting Clock buffer for port CLK_20M_SMP_I,TNM=CLK_20M_SMP_I

  Inserting Clock buffer for port CPU_WR_N_I,TNM=CPU_WR_N_I

  Inserting Clock buffer for port CLK_40M_P_I,TNM=CLK_40M_P_I

  Inserting Clock buffer for port CLK_40M_S2_I,TNM=CLK_40M_S2_I



Net buffering Report:

No nets needed buffering.





------------------------------------------

Timing reports

   Delay - This is the delay from a start point

           such as a register or primary input.

   Slack - If this value is negative then it indicates

           the size of the timing violation.

   FO    - This is the estimated fanout or loading

           used in calculating net delays





-------------------------------------------

Requested default timing:

      Frequency=15.0 MHz, Period=66.7 ns

Estimated result:

      Frequency=16.7 MHz, Period=60.0 ns

      Slack on longest path: 6.7 ns



Timing Information for Longest Paths:



Instance: Z_40ACCCHIPZ_32TXD2PZ_41.base0_reg20[12], cell DFFRE

  D I -Z_40ACCCHIPZ_32TXD2PZ_41.sync_tx20_0_base0_reg20_4[12]Delay=60.4,

  Slack=6.7

Instance: Z_40ACCCHIPZ_32TXD2PZ_41.base0_reg20[18], cell DFFRE

   D I -Z_40ACCCHIPZ_32TXD2PZ_41.sync_tx20_0_base0_reg20_4[18]Delay=59.8,

   Slack=7.3 

Instance: Z_40ACCCHIPZ_32TXD2PZ_41.base0_reg20[15], cell DFFRE

   D I -Z_40ACCCHIPZ_32TXD2PZ_41.sync_tx20_0_base0_reg20_4[15]Delay=59.0,

   Slack=8.1 

Instance: Z_40ACCCHIPZ_32TXD2PZ_41.base3_reg20[15], cell DFFRE

   D I - Z_40ACCCHIPZ_32TXD2PZ_41.N_1956Delay=58.6, Slack=8.5 

Instance: Z_40ACCCHIPZ_32TXD2PZ_41.base0_reg20[11], cell DFFRE

   D I -Z_40ACCCHIPZ_32TXD2PZ_41.sync_tx20_0_base0_reg20_4[11]Delay=58.4,

   Slack=8.7 

Instance: Z_40ACCCHIPZ_32TXD2PZ_41.base3_reg20[13], cell DFFRE

   D I -Z_40ACCCHIPZ_32TXD2PZ_41.sync_tx20_3_base3_reg20_4[13]Delay=58.3,

   Slack=8.8 

Instance: Z_40ACCCHIPZ_32TXD2PZ_41.base1_reg20[13], cell DFFRE

   D I -Z_40ACCCHIPZ_32TXD2PZ_41.sync_tx20_1_base1_reg20_4[13]Delay=58.3,

   Slack=8.8 

.

.

.

.

---------------------------------------

Resource Usage Report



Mapping to part: 40125xvbg560-1

I/O primitives:

OBUF           98 uses

IBUF           43 uses

OUTFF INIT=R   14 uses

INFF INIT=R    10 uses



BUFG           4 uses



Carry primitives used for arithmetic functions:

INC-FG-1       11 uses

INC-FG-CI      121 uses

FORCE-0        14 uses

ADD-FG-CI      183 uses

EXAMINE-CI     55 uses

FORCE-1        30 uses

ADD-G-F1       4 uses

SUB-FG-CI      180 uses

DEC-FG-0       3 uses

DEC-FG-CI      12 uses



Register bits not including I/Os:   1258

Logic Mapping Summary:

FMAPs: 3059 of 9248 (34%)

HMAPs: 647 of 4624 (14%)

Total packed CLBs: 1530 of 4624 (34%)

(Packed CLBs is determined by the larger of three quantities:

   Registers / 2, HMAPs, or FMAPs / 2.)



Mapper successful!

Process took 169.984 seconds realtime, 169.984 seconds cputime

Exemplar Logic

The area section of the Exemplar Logic report includes area utilization information for FMAPs, HMAPs, CLBs, IO buffers, and IOB registers. The timing section of the report lists the predicted timing of the critical path, and shows the number of levels of logic and buffers.

Summary Report

Content-Type: text/plain; charset="us-ascii"

Content-Disposition: attachment; filename="ram.sum"





*******************************************************



Cell: mem    View: behav    Library: work



*******************************************************



Total accumulated area : 

 Number of FG Function Generators :      4

 Number of Packed CLBs :                 1

 Number of IBUF :                        9

 Number of OBUF :                        1

 Number of IOB Output Flip Flops :       2



 Number of ports :                      10

 Number of nets :                       24

 Number of instances :                  17

 Number of references to this view :     0





            Cell          Library  References     Total Area



         F2_LUT            xi4ex     2 x      1      2 FG Function Generators

          OFDTX            xi4ex     2 x      1      2 IOB Output Flip Flops

           OBUF            xi4ex     1 x      1      1 OBUF

            GND            xi4ex     1 x      1      1 GND

           IBUF            xi4ex     9 x      1      9 IBUF

       RAM16x1S            xi4ex     2 x      1      2 FG Function Generators



Using wire table: 4052ex-3_avg





                        Slack Table at End Points





End points                         Slack       Arrival             Required

                                             rise     fall      rise     fall



ix328_l5_1_l0_l0_0_l0_l0/D     :    n/a      20.02   20.92      n/a      n/a 

ix328_l5_0_l0_l0_0_l0_l0/D     :    n/a      20.02   20.92      n/a      n/a 

dio(0)/                        :    n/a      15.90   16.80      n/a      n/a 

dio(1)/                        :    n/a      15.90   16.80      n/a      n/a 

ix328_l5_1_l0_l0_0_l0_l0/WE    :    n/a      11.80   11.80      n/a      n/a 

ix328_l5_0_l0_l0_0_l0_l0/WE    :    n/a      11.80   11.80      n/a      n/a 

ix328_reg_q(1)_O1/D            :    n/a      9.12   9.12        n/a      n/a 

ix328_reg_q(0)_O1/D            :    n/a      9.12   9.12        n/a      n/a 

ro/                            :    n/a      8.55   8.55        n/a      n/a 

ix328_l5_0_l0_l0_0_l0_l0/WCLK  :    n/a      7.06   7.06        n/a      n/a 







                        Critical Path Report



Critical path #1, (unconstrained path)

NAME                           GATE         ARRIVAL              LOAD

-------------------------------------------------------------------------

we/                                         0.00 up             2.32

ix351/O                         IBUF        4.12 up             2.94

ix328_nx4/O                     F2_LUT      8.86 up             2.94

ix328_reg_q(0)_O1/O             OFDTX      16.80 dn             2.94

ix328_reg_q(0)_I1/O             IBUF       18.60 dn             2.32

ix328_l5_0_l0_l0_0_l0_l0/D      RAM16x1S   20.92 dn             0.00

data arrival time                         20.92





data required time                                          not specified

-------------------------------------------------------------------------

data required time                                          not specified

data arrival time                                           20.92

                                                          ----------

                                                       unconstrained path

-------------------------------------------------------------------------





Critical path #2, (unconstrained path)

NAME                          GATE         ARRIVAL              LOAD

-------------------------------------------------------------------------

meme/                                      0.00 up             2.32

ix352/O                       IBUF        4.12 up             2.94

ix328_nx4/O                   F2_LUT      8.86 up             2.94

ix328_reg_q(0)_O1/O          OFDTX       16.80 dn             2.94

ix328_reg_q(0)_I1/O          IBUF        18.60 dn             2.32

ix328_l5_0_l0_l0_0_l0_l0/D   RAM16x1S    20.92 dn             0.00

data arrival time                        20.92





data required time                                          not specified

-------------------------------------------------------------------------

data required time                                          not specified

data arrival time                                           20.92

                                                          ----------

                                                       unconstrained path

-------------------------------------------------------------------------





.

.

.

.

Log Report



Content-Type: text/plain; charset="us-ascii"

Content-Disposition: attachment; filename="ram.log"



C:\Program Files\Exemplar Logic\Galileo 4.2\bin\win32\gc.exe \

F:/rel4.2/example/ram.vhd F:/rel4.2/example/ram.edf -input_format=VHDL \

-target=xi4ex -output_format=EDIF -area -effort=quick \

-edif_timing_file=F:/rel4.2/example/ram.tim -encoding=OneHot -wire_tree=Worst \

-nocontrol -vhdl_93 -process=3 -wire_table=4052ex-3_avg -chip 

-------------------------------------------------

Galileo - V4.2 (build 2.01, compiled Dec 19 1997 at 16:48:48)

Copyright 1990-1996 Exemplar Logic, Inc.  All rights reserved.



Checking Security ...

Info: setting encoding to OneHot

Info: setting process to 3

Info: setting wire_tree to Worst

Info: setting wire_table to 4052ex-3_avg

--

-- Welcome to Galileo

-- Run By massoumi@WACO

-- Run Started On Tue Jan 13 11:05:09 Pacific Daylight Time 1998

--

-- read -format VHDL {F:/rel4.2/example/ram.vhd}

-- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.2\data\standard.vhd for unit standard

-- Loading package standard into library std

-- Reading vhdl file F:/rel4.2/example/ram.vhd into library work

-- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.2\data\std_1164.vhd for unit std_logic_1164

-- Loading package std_logic_1164 into library ieee

-- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.2\data\ex_1164.vhd for unit exemplar_1164

-- Loading package exemplar_1164 into library exemplar

-- Reading file C:\PROGRA~1\EXEMPL~1\GALILE~1.2\data\exemplar.vhd for unit exemplar

-- Loading package exemplar into library exemplar

-- Loading package my_pkg into library work

-- Loading entity mem into library work

-- Loading architecture behav of mem into library work

"F:/rel4.2/example/ram.vhd",line 20: Warning, output ro is never assigned a value.

-- Compiling root entity mem(behav)

-- Reading target technology xi4ex

Reading library file `C:\PROGRA~1\EXEMPL~1\GALILE~1.2\lib\xi4ex.syn`...

Library version = 0.9

Delays assume: Process=3 

-- Pre Optimizing Design .work.mem.behav

INFO: Using Ram Cell ram_io_inclock_outclock_2_3_8.

-- Read Module Generators

-- Reading module generator description from file C:\PROGRA~1\EXEMPL~1\GALILE~1.2\data\modgen\xi4e.vhd

-- Reading vhdl file C:\PROGRA~1\EXEMPL~1\GALILE~1.2\data\modgen\xi4e.vhd into library OPERATORS

-- Modgen File xi4e.vhd Version 4.20

-- Resolving Modgen With modgen_select "small"

-- Start module generator resolving for design .work.mem.behav

-- Resolving function ram_io with module generator ram_io_2_3_8_true_true_false  from file xi4e.vhd

-- optimize -target xi4ex -effort quick -chip -area

-- Start optimization for design .work.mem.behav

Using wire table: 4052ex-3_avg

                                                              

      Pass     Area    Delay     DFFs  PIs   POs --CPU--

               (FGs)    (ns)                      min:sec

      1          2       17         2     7     3   00:00 

Info, setting outputs in top level view 'behav' to fast.

Using wire table: 4052ex-3_avg

-- Start timing optimization for design .work.mem.behav



Latest arrival time at primary output: 20.9 ns

Latest arrival time at register input: 20.9 ns



Forcing timing constraints at all end points: 18.8 ns



Initial Timing Optimization Statistics:

---------------------------------------



Most Critical Slack    :       -2.1

Sum of Negative Slacks :       -4.2

Longest Path           :       20.9 ns

Area                   :        2.0





                                                             

Final Timing Optimization Statistics:

-------------------------------------



Most Critical Slack    :       -2.1

Sum of Negative Slacks :       -4.2

Longest Path           :       20.9 ns

Area                   :        2.0



Total time taken : 0 cpu secs

Using wire table: 4052ex-3_avg

-- Start timespec generation for design .work.mem.behav



*******************************************************



Cell: mem    View: behav    Library: work



*******************************************************



 Number of ports :                      10

 Number of nets :                       24

 Number of instances :                  17

 Number of references to this view :     0



Total accumulated area : 

 Number of FG Function Generators :      4

 Number of Packed CLBs :                 1

 Number of IBUF :                        9

 Number of OBUF :                        1

 Number of IOB Output Flip Flops :       2



-- Writing file F:/rel4.2/example/ram.edf

-- CPU time taken for this run was 29.55 sec

-- Run ended On Tue Jan 13 11:05:37 Pacific Daylight Time 1998

-- Galileo run successfully completed.  Goodbye !

Synopsys FPGA Express

FPGA Express™ reports include information on the following.