Installing Design Examples and Tactical Software

Synthesis and Simulation Design GuideChapter 1: Getting Started

Installing Design Examples and Tactical Software

The information in this manual supplements information in your synthesis and HDL simulator manuals. Before you start designing Xilinx FPGAs, read the Xilinx-specific information in your HDL manuals. Also, read and follow the instructions in the latest version of the Quick Start Guide for Xilinx Alliance Series, as well as the current version of the Alliance Series Install and Release Document.

This manual includes numerous HDL design examples created with VHDL and Verilog. VHDL is more comprehensive than Verilog, and you many need to spend more time learning how to apply VHDL constructs to synthesis.

Software Requirements

To synthesize, simulate, and implement the design examples in this manual, you should have the current versions of your synthesis and simulation software, as well as the Alliance Series 2.1 or later version of the Xilinx Development System installed on your system.

Memory Requirements

The values provided in the following table are for typical designs, and include loading the operating system. Additional memory may be required for certain “boundary-case” or unusual designs, as well as for the concurrent operation of other applications (for example, synthesis or HDL simulation). Xilinx recommends compiling XC4000EX/ XL designs on the Ultra Sparc, HP715, or equivalent workstations. Although 64 MB of RAM and 64 MB of swap space are required to compile XC4000EX designs, Xilinx recommends that you use 128 MB of RAM and 128 MB of swap space for more efficient processing of your XC4000EX designs.

Table 1_1 Memory Requirements for Workstations and PCs

Xilinx Device	RAM	Swap Space
XC3000A/L XC3100A/L XC4000E/L XC4028EX through XC4036EX XC4002XL through XC4028XL XCS (Spartan) XC5200 XC9500 (small devices)	64 MB	64 MB - 128 MB
XC4036XL through XC4062XL XC9500 (large devices)	128 MB	128 MB - 256 MB
XC4085XL XC40125XV	256 MB	256 MB - 512 MB

Disk Space Requirements

Before you install the programs and files, verify that your system meets the requirements listed in the following table for the applicable options. The disk space requirements listed are approximations and may not exactly match the actual numbers. To significantly reduce the amount of disk space needed, install only the components and documentation that you will actually use. In the following table, the Data column represents files that are common to all three workstation platforms. For example, for a Solaris machine, you need ~ 110 (12 plus 98) MB of disk space.

Note: Refer to the Alliance Series Install and Release Document for more information on disk space requirements.

Table 1_2 Disk Space Requirements

Software Component	Data	Sol	HP
Xilinx Core Technology	~12 MB	~98 MB	~108 MB
Xilinx Device Data Files (All devices)^a	~195 MB	~26 MB	~26 MB
Documentation: Online Help Documentation Browser Xilinx Tutorial Files Xilinx Userware	~30 MB total ~17 MB ~1 MB ~4 MB	~10 MB	~10 MB
a. The memory requirements specified are for the installation of all Xilinx devices. You can significantly reduce the amount of disk space required by installing only the files for the devices you want to target.

Xilinx Internet Site

To download the programs and files from the Xilinx Internet Site, you must meet the disk requirements listed in the following table.

Table 1_3 Internet Files

Directory/Location	Description	Compressed File	Directory Size
M1_VHDL_source^a	All VHDL source code only (no scripts, compilation, or implementation files)	m1_vhdl_src.tar.Z (size: 60 KB) or m1_vhdl_src.zip (size: 68 KB)	271 KB
M1_Verilog_source^a	All Verilog source code only (no scripts, compilation, or implementation files)	m1_verilog_src.tar.Z (size: 57 KB) or m1_verilog_src.zip (size: 64 KB)	256 KB
M1_HDL_source^a	All VHDL and Verilog source code only (no scripts, compilation, or implementation files)	m1_hdl_src.tar.Z (size: 110 KB) or m1_hdl_src.zip (size: 129 KB)	497 KB
a. These files are located at ftp://ftp.xilinx.com/pub/applications/3rdparty

Retrieving Tactical Software and Design Examples

You can retrieve the HDL design examples from the Xilinx Internet Site. If you need assistance retrieving the files, use the information listed in the “Technical Support” section of this chapter to contact the Xilinx Hotline.

You must install the retrieved files on the same system as the Xilinx software and the synthesis and simulation tools. However, do not install the files into the directory with the current release of the software since they may get overwritten during the installation of the next version of the software.

From Xilinx Internet FTP Site

You can retrieve the programs and files from the Xilinx Internet FTP (File Transfer Protocol) site. Alternatively, if you are not familiar with FTP, you can retrieve the files by going to the Xilinx Web site (http://www.xilinx.com), clicking on Service and Support, and using the File Download option. To access the Xilinx FTP Site, you must either have an internet-capable FTP utility available on your machine or a Web browser that has FTP. To use FTP, your machine must be connected to the Internet and you must have permission to use FTP on remote sites. If you need more information on this procedure, contact your system administrator.

To retrieve the programs and files from the Xilinx FTP site, use the following procedure.

Go to the directory on your local machine where you want to download the files, as follows.

cd directory
Invoke the FTP utility or your Web browser that provides FTP.
Connect to the Xilinx FTP site, ftp.xilinx.com as follows.

ftp> open ftp.xilinx.com

or

Enter the following URL.

ftp://ftp.xilinx.com
Log into a guest account if the FTP utility or Web browser does not perform this automatically. This account gives you download privileges.

Name (machine:user-name): anonymousGuest login ok, send your complete e-mail address as the password. Password:your_email_address
Go to the following directory.

ftp> cd pub/applications/3rdparty
If you are using an FTP utility, make sure you are in binary mode.

ftp> bin
Retrieve the appropriate design files as follows.

ftp> get design_files.tar.Z

or

ftp> get design_files.zip

or

Select the appropriate file and select a destination directory on your local machine.
Extract the files as described in the next section.

Extracting the Files

You must install the retrieved files on the same system as the current release of the Xilinx software and the synthesis and simulation tools. However, do not install the files in the directory with the current software because they may get overwritten during the installation of the
next version of the software. The files are stored in the UNIX^™ standard tar and compress form, as well as in the PC^™ standard zip form. To extract the files, use one of the following procedures.

Note: If the following procedures do not work on your system, consult your system administrator for help on extracting the files.

Extracting .tar.Z File in UNIX

Go to the directory where you downloaded the files.

cd downloaded_files
Uncompress the files.

uncompress design.tar.Z
Extract the files.

tar xvf design.tar

Extracting .zip File in UNIX

Go to the directory where you downloaded the files.

cd downloaded_files
Uncompress the files.

unzip design.zip

Extracting .zip File in MS-DOS

Go to the directory where you downloaded the files:

cd downloaded_files
Uncompress the files:

pkunzip -d design.zip

Directory Tree Structure

After you have completed the installation, you should have the following directory tree structure.

5k_preset

    /VHDL

    /Verilog

/Async_RAM_as_latch

    /VHDL

    /Verilog

/Barrel_SR

    /VHDL

        /Barrel

        /Barrel_Org

    /Verilog

        /Barrel

        /Barrel_Org

/Bidir_LogiBLOX

    /VHDL

    /Verilog

/Bidir_infer

    /VHDL

    /Verilog

/Bidir_instantiate

    /VHDL

    /Verilog

/Bnd_scan_4k

    /VHDL

    /Verilog

/Bnd_scan_5k

    /VHDL

    /Verilog

/Case_vs_if

    /VHDL

        /Case_ex

        /If_ex

    /Verilog

        /Case_ex

        /If_ex

/Clock_enable

    /VHDL

    /Verilog

/Clock_mux

    /VHDL

    /Verilog

/Constants

    /VHDL

    /Verilog

        /Parameter1

        /Parameter2

/D_latch

    /VHDL

    /Verilog

/D_register

    /VHDL

    /Verilog

/FF_example

    /VHDL

    /Verilog

/GR_5K

    /VHDL

        /Active_low_GR

        /No_GR

        /Use_GR

    /Verilog

        /Active_low_GR

        /No_GR

        /Use_GR

/GSR

    /VHDL

        /Active_low_GSR

        /No_GSR

        /Use_GSR

    /Verilog

        /Active_low_GSR

        /No_GSR

        /Use_GSR

/Gate_clock

    /VHDL

        /Gate_clock

        /Gate_clock2

    /Verilog

        /Gate_clock

        /Gate_clock2

/IO_Decoder

    /VHDL

    /Verilog

/LogiBLOX_DP_RAM

    /VHDL

    /Verilog

/LogiBLOX_SR

    /VHDL

    /Verilog

/Mux_vs_3state

    /VHDL

        /Mux_gate

        /Mux_gate16

        /Mux_tbuf

        /Mux_tbuf16

    /Verilog

        /Mux_gate

        /Mux_gate16

        /Mux_tbuf

        /Mux_tbuf16

/Nested_if

    /VHDL

        /If_case

        /Nested_if

    /Verilog

        /If_case

        /Nested_if

/OMUX_example

    /VHDL

    /Verilog

/RAM_primitive

    /VHDL

    /Verilog

/ROM_RTL

    /VHDL

    /Verilog

/Res_sharing

    /VHDL

        /Res_no_share

        /Res_sharing

    /Verilog

        /Res_no_share

        /Res_sharing

/Set_and_Reset

    /VHDL

    /Verilog

/Sig_vs_Var

    /VHDL

        /Xor_Sig

        /Xor_Var

/State_Machine

    /VHDL

        /Binary

        /Enum

        /One_Hot

    /Verilog

        /Binary

        /Enum

        /One_Hot

/Unbonded_IO

    /VHDL

    /Verilog