Placing and Routing Your Design

Note: For more information on placing and routing your design, refer to the Development System Reference Guide.

The overall goal when placing and routing your design is fast implementation and high-quality results. However, depending on the situation and your design, you may not always accomplish this goal, as described in the following examples.

• Earlier in the design cycle, run time is generally more important than the quality of results, and later in the design cycle, the converse is usually true.
  
  
• During the day, you may want the tools to quickly process your design while you are waiting for the results. However, you may be less concerned with a quick run time, and more concerned about the quality of results when you run your designs for an extended period of time (during the night or weekend).
  
  
• If the targeted device is highly utilized, the routing may become congested, and your design may be difficult to route. In this case, the placer and router may take longer to meet your timing requirements.
  
  
• If design constraints are rigorous, it may take longer to correctly place and route your design, and meet the specified timing.
  
  

Decreasing Implementation Time

The options you select for the placement and routing of your design directly influence the run time. Generally, these options decrease the run time at the expense of the best placement and routing for a given device. Select your options based on your required design performance.

Note: If you are using the command line, the appropriate command line option is provided in the following procedure.

Use the following steps to decrease implementation time in the Design Manager.

1. Select Design Implement
   
   The Implement dialog box appears.
   
   
2. Select the Options button in the Implement dialog box.
   
   The Options dialog box appears.
   
   
3. Select the Edit Template button next to the Implementation drop-down list in the Program Options Templates field. The Implementation Template dialog box appears.
   
   
4. Select the Place & Route tab.
   
   
5. Set options in this dialog box as follows.
   
   
   • Place & Route Effort Level
     
     Generally, you can reduce placement times by selecting a less CPU-intensive algorithm for placement. You can set the placement level from 1 (fastest run time) to 5 (best results) with the default equal to 2. Use the -l switch at the command line to perform the same function.
     
     

     Note: In some cases, poor placement with a lower placement level setting can result in longer route times.

   • Router Options
     
     You can limit router iterations to reduce routing times. However, this may prevent your design from meeting timing requirements, or your design may not completely route. From the command line, you can control router passes with the -i switch.
     
     
   • Use Timing Constraints During Place and Route
     
     You can improve run times by not specifying some or all timing constraints. This is useful at the beginning of the design cycle during the initial evaluation of the placed and routed circuit. To disable timing constraints in the Design Manager, deselect the Use Timing Constraints During Place and Route button. To disable timing constraints at the command line, use the -x switch with PAR.
     
     
6. Select OK to exit the Implementation Template dialog box.
   
   
7. Select any applicable options in the Options dialog box.
   
   
8. Select OK.
   
   
9. Select Run in the Implement dialog box to begin implementing your design.
   
   

Improving Implementation Results

Conversely, you can select options that increase the run time, but produce a better design. These options generally produce a faster design at the cost of a longer run time. These options are useful when you run your designs for an extended period of time (overnight or over the weekend).

Multi-Pass Place and Route Option

Use this option to place and route your design with several different cost tables (seeds) to find the best possible placement for your design. This optimal placement results in shorter routing delays and faster designs. This option works well when the router passes are limited (with the -i option). After an optimal cost table is selected, use the re-entrant routing feature to finish the routing of your design. You may select this option from the Design menu in the Design Manager, or specify this option at the command line with the -n switch.

Turns Engine Option (UNIX only)

This option is a Unix-only feature that works with the Multi-Pass Place and Route option to allow parallel processing of placement and routing on several Unix machines. The only limitation to how many cost tables are concurrently tested is the number of workstations you have available. To use this option in the Design Manger, specify a node list when selecting the Multi-Pass Place and Route option. To use this feature at the command line, use the -m switch to specify a node list, and the -n switch to specify the number of place and route iterations.

Note: For more information on the turns engine option, refer to the Xilinx Development System Reference Guide.

Re-entrant Routing Option

Use the re-entrant routing option to further route an already routed design. The router reroutes some connections to improve the timing or to finish routing unrouted nets. You must specify a placed and routed design (.ncd) file for the implementation tools. This option is best used when router iterations are initially limited, or when your design timing goals are close to being achieved.

To initiate a re-entrant route from the Design Manager interface, follow these steps.

1. From the Design Manager, select the placed and routed design revision for the re-entrant option.
   
   
2. Select Tools Flow Engine to start the Flow Engine from the Design Manager.
   
   
3. From the Flow Engine menu, select Setup Re-entrant Route.
   
   
4. In the Advanced dialog box that is displayed, select the Allow Re-entrant Routing option.
   
   
5. Select the appropriate options in the Re-entrant Route Options field.
   
   
6. Select OK.
   
   
7. The Place and Route icon in the Flow Engine is replaced with the Re-entrant Route icon. If this step is completed, use the Step Back button until the Re-entrant Route icon no longer indicates completed.
   
   
8. Select Run to complete the re-entrant routing.
   
   

To initiate a re-entrant route from the command line, you can run PAR with the -k and -p options, as well as any other options you want to use for the routing process. You must either specify a unique name for the post re-entrant routed design (.ncd) file or use the -w switch to overwrite the previous design file, as shown in the following examples.

par -k -p other_options design_name.ncd new_name.ncd

par -k -p -w other_options design_name.ncd design.ncd

Cost-Based Clean-up Option

This option specifies clean-up passes after routing is completed to substitute more appropriate routing options available from the initial routing process. For example, if several local routing resources are used to transverse the chip and a longline is available, the longline is substituted in the clean-up pass. The default value of cost-based cleanup passes is 1. To change the default value, use the Template Manager in the Design Manager, or the -c switch at the command line.

Delay-Based Clean-up Option

This option specifies clean-up passes after routing is completed to substitute more appropriate routing options to reduce delays. The default number of passes for delay-based clean-up is 0. You can change the default in the Design Manager in the Implementation Options window, or at the command line with the -d switch.

Guide Option (not recommended)

This option is generally not recommended for synthesis-based designs. Re-synthesizing modules can cause the signal and instance names in the resulting netlist to be significantly different from those in earlier synthesis runs. This can occur even if the source level code (Verilog or VHDL) contains only a small change. Because the guide process is dependent on the names of signals and comps, synthesis designs often result in a low match rate during the guiding process. Generally, this option does not improve implementation results.