Evaluating your Design for Coding Style and System Features

At this point, if you are not satisfied with your design performance, you can re-evaluate your code and make any necessary improvements. Modifying your code and selecting different compiler options can dramatically improve device utilization and speed.

Tips for Improving Design Performance

This section includes ways of improving design performance by modifying your code and by incorporating FPGA system features. Most of these techniques are described in more detail in this manual.

Modifying Your Code

You can improve design performance with the following design modifications.

• Reduce levels of logic to improve timing
  
  
• Redefine hierarchical boundaries to help the compiler optimize design logic
  
  
• Pipeline
  
  
• Logic replication
  
  
• Use of LogiBLOX or Coregen modules
  
  
• Resource sharing
  
  
• Restructure logic
  
  

Using FPGA System Features

After correcting any coding style problems, use any of the following FPGA system features in your design to improve resource utilization and to enhance the speed of critical paths.

Note: Each device family has a unique set of system features. Review the current version of the The Programmable Logic Data Book for the system features available for the device you are targeting.

• Use global set/reset and global tri-state nets to reduce routing congestion and improve design performance
  
  
• Use clock enables
  
  
• Place the highest fanout signals on the global buffers
  
  
• Modify large multiplexers to use tri-state buffers
  
  
• Use one-hot encoding for large or complex state machines
  
  
• Use I/O registers when applicable
  
  
• Use I/O decoders when applicable
  
  
• Use I/O multiplexers when applicable
  
  

Using Xilinx-specific Features of Your Synthesis Tool

Most synthesis tools have special options for the Xilinx-specific features listed in the previous section. Refer to your synthesis tool documentation for help on using Xilinx-specific features.