Using Global Low-skew Clock Buffers

Synthesis and Simulation Design GuideChapter 4: Designing FPGAs with HDL

Using Global Low-skew Clock Buffers

For designs with global signals, use global clock buffers to take advantage of the low-skew, high-drive capabilities of the dedicated global buffer tree of the target device. When you use the Insert Pads or equivalent command, your synthesis tool automatically inserts a BUFG generic clock buffer whenever an input signal drives a clock signal. The Xilinx implementation software automatically selects the clock buffer that is appropriate for your specified design architecture. If you want to use a specific global buffer, you must instantiate it. Many synthesis tools automatically insert I/O pins and clock buffers. Also, some synthesis tools limit I/O and global buffers. Refer to your synthesis tool documentation for detailed information.

You can instantiate an architecture-specific buffer if you understand the architecture and want to specify how the resources should be used. Each XC4000E/L and Spartan device contains four primary and four secondary global buffers that share the same routing resources. XC4000EX/XLA/XL/XV devices have sixteen global buffers; each buffer has its own routing resources. XC5200 devices have four dedicated global buffers in each corner of the device.

XC4000 EX/XLA/XL/XV devices have two different types of global buffer, Global Low-Skew Buffers (BUFGLS) and Global Early Buffers (BUFGE). Global Low-Skew Buffers are standard global buffers that should be used for most internal clocking or high fanout signals that must drive a large portion of the device. There are eight BUFGLS buffers available, two in each corner of the device. The Global Early Buffers are designed to provide faster clock access, but CLB access is limited to one quadrant of the device. I/O access is also limited. Similarly, there are eight BUFGEs, two in each corner of the device.

Because Global Early and Global Low-Skew Buffers share a single pad, a single IPAD can drive a BUFGE, BUFGLS, or both in parallel. The parallel configuration is especially useful for clocking the fast capture latches of the device. Since the Global Early and Global Low-Skew Buffers share a common input, they cannot be driven by two different signals.

You can use the following criteria to help select the appropriate global buffer for a given design path.

The simplest option is to use a Global Low-Skew Buffer.
If you want a faster clock path, use a BUFG. Initially, the software will try to use a Global Low-Skew Buffer. If timing requirements are not met, a BUFGE is automatically used if possible.
If a single quadrant of the chip is sufficient for the clocked logic, and timing requires a faster clock than the Global Low-Skew Buffer, use a Global Early Buffer.

Note: For more information on using the XC4000 EX/XLA/XL/XV device family global buffers, refer to the online version of The Programmable Logic Data Book or the Xilinx web site at http://www.xilinx.com.

For XC4000E/L and Spartan devices, you can use secondary global buffers (BUFGS) to buffer high-fanout, low-skew signals that are sourced from inside the FPGA. To access the secondary global clock buffer for an internal signal, instantiate the BUFGS cell. You can use primary global buffers (BUFGP) to distribute signals applied to the FPGA from an external source. Internal signals can be globally distributed with a primary global buffer, however, the signals must be driven by an external pin.

Some synthesis tools limit I/O or BUFG resources. For example, BUFG does not synthesize to more than eight instances depending on the selected device architecture. However, some tools do not use all your available resources. Compiling modules separately may also result in resource over-utilization. Check with your synthesis vendor.

XC4000E/L and Spartan devices have four primary (BUFGP) and four secondary (BUFGS) global clock buffers that share four global routing lines, as shown in the following figure.

Figure 4.1 Global Buffer Routing Resources (XC4000E, Spartan)

These global routing resources are only available for the eight global buffers. The eight global nets run horizontally across the middle of the device and can be connected to one of the four vertical longlines that distribute signals to the CLBs in a column. Because of this arrangement only four of the eight global signals are available to the CLBs in a column. These routing resources are “free” resources because they are outside of the normal routing channels. Use these resources whenever possible. You may want to use the secondary buffers first because they have more flexible routing capabilities.

You should use the global buffer routing resources primarily for high-fanout clocks that require low skew, however, you can use them to drive certain CLB pins, as shown in the following figure. In addition, you can use these routing resources to drive high-fanout clock enables, clear lines, and the clock pins (K) of CLBs and IOBs.

In the following figure, the C pins drive the input to the H function generator, Direct Data-in, Preset, Clear, or Clock Enable pins. The F and G pins are the inputs to the F and G function generators, respectively.

Figure 4.2 Global Longlines Resource CLB Connections

If your design does not contain four high-fanout clocks, use these routing resources for signals with the next highest fanout. To reduce routing congestion, use the global buffers to route high-fanout signals. These high-fanout signals include clock enables and reset signals (not global reset signals). Use global buffer routing resources to reduce routing congestion; enable routing of an otherwise unroutable design; and ensure that routing resources are available for critical nets.

Xilinx recommends that you assign up to four secondary global clock buffers to the four signals in your design with the highest fanout (such as clock nets, clock enables, and reset signals). Clock signals that require low skew have priority over low-fanout non-clock signals. You can source the signals with an input buffer or a gate internal to the design. Generate internally sourced clock signals with a register to avoid unwanted glitches. The synthesis tool can insert global clock buffers or you can instantiate them in your HDL code.

Note: Use Global Set/Reset resources when applicable. Refer to the “Using Dedicated Global Set/Reset Resource” section in this chapter for more information.

Inserting Clock Buffers

Many synthesis tools automatically insert a secondary global clock buffer on all input ports that drive a register's clock pin or a gated clock signal. Refer to your synthesis tool documentation for information on disabling the automatic insertion of clock buffers, and how to specify which ports have clock buffers.

Instantiating Global Clock Buffers

You can instantiate global buffers in your code as described in this section.

Instantiating Buffers Driven from a Port

You can instantiate global buffers and connect them to high-fanout ports in your code rather than inferring them from a synthesis tool script. If you do instantiate global buffers, verify that the Pad parameter is not specified for the buffer.

Instantiating Buffers Driven from Internal Logic

Some synthesis tools require you to instantiate a global buffer in your code to use the dedicated routing resource if a high-fanout signal is sourced from internal flip-flops or logic (such as a clock divider or multiplexed clock), or if a clock is driven from the internal oscillator or non-dedicated I/O pin. The following VHDL and Verilog examples instantiate a BUFGS for an internal multiplexed clock circuit. A Set Dont Touch or equivalent attribute is added to the instantiated component to prevent further optimization by the synthesizer.

VHDL Example

-----------------------------------------------

-- CLOCK_MUX.VHD Version 1.1                 --

-- This is an example of an instantiation of --

-- global buffer (BUFGS) from an internally  --

-- driven signal, a multiplexed clock.       --

-- March 1998                                --

-----------------------------------------------



library IEEE;

use IEEE.std_logic_1164.all;



entity clock_mux is

    port (DATA, SEL:              in  STD_LOGIC;

          SLOW_CLOCK, FAST_CLOCK: in  STD_LOGIC;

          DOUT:                   out STD_LOGIC);

end clock_mux;



architecture XILINX of clock_mux is



signal CLOCK:      STD_LOGIC;

signal CLOCK_GBUF: STD_LOGIC;



component BUFGS 

    port (I: in  STD_LOGIC; 

          O: out STD_LOGIC);

end component;



begin



Clock_MUX: process (SEL, FAST_CLOCK, SLOW_CLOCK)

    begin

        if (SEL = '1') then

                CLOCK <= FAST_CLOCK;

        else

            CLOCK <= SLOW_CLOCK;

        end if;

    end process;



GBUF_FOR_MUX_CLOCK: BUFGS 

    port map (I => CLOCK, 

              O => CLOCK_GBUF);



Data_Path: process (CLOCK_GBUF)

    begin

        if (CLOCK_GBUF'event and CLOCK_GBUF='1') then

            DOUT <= DATA;

        end if;

    end process;



end XILINX;

Verilog Example

      ///////////////////////////////////////////////

     // CLOCK_MUX.V Version 1.1                   //

    // This is an example of an instantiation of //

   // global buffer (BUFGS) from an internally  //

  // driven signal, a multipled clock.         //

 // March 1998                                //

///////////////////////////////////////////////



module clock_mux (DATA, SEL, SLOW_CLOCK, FAST_CLOCK,

                  DOUT);



    input  DATA, SEL;

    input  SLOW_CLOCK, FAST_CLOCK;

    output DOUT;



    reg   CLOCK;

    wire   CLOCK_GBUF;

    reg    DOUT;



    always @ (SEL or FAST_CLOCK or SLOW_CLOCK)

    begin

        if (SEL == 1'b1)

            CLOCK <= FAST_CLOCK;

        else

            CLOCK <= SLOW_CLOCK;

    end



    BUFGS GBUF_FOR_MUX_CLOCK (.O(CLOCK_GBUF),

                              .I(CLOCK));



    always @ (posedge CLOCK_GBUF)

        DOUT = DATA;



endmodule