|
|
|
|
|
XC4000 and Spartan devices have a dedicated Global Set/Reset (GSR) net that you can use to initialize all CLBs and IOBs. When the GSR is asserted, every flip-flop in the FPGA is simultaneously preset or cleared. You can access the GSR net from the GSR pin on the STARTUP block or the GSRIN pin of the STARTBUF (VHDL).
Since the GSR net has dedicated routing resources that connect to the Preset or Clear pin of the flip-flops, you do not need to use general purpose routing or global buffer resources to connect to these pins. If your design has a Preset or Clear signal that affects every flip-flop in your design, use the GSR net to increase design performance and reduce routing congestion.
The XC5200 family has a dedicated Global Reset (GR) net that resets all device registers. As in the XC4000 and Spartan devices, the STARTUP or STARTBUF (VHDL) block must be instantiated in your code in order to access this resource. The XC3000A devices also have dedicated Global Reset (GR) that is connected to a dedicated device pin (see device pinout). Since this resource is always active, you do not need to do anything to activate this feature.
For XC4000, Spartan, and XC5200 devices, the Global Set/Reset (GSR or GR) signal is, by default, set to active high (globally resets device when logic equals 1). If you are using an older version of a synthesis tool, for an active low reset, instantiate an inverter in your code to invert the global reset signal. The inverter is absorbed by the STARTUP block and does not use any device resources (function generators). For older versions of synthesis tools, although the inverted signal may be behaviorally described in your code, Xilinx recommends instantiating the inverter to prevent the mapping of the inverter into a CLB function generator, and subsequent delays to the reset signal and unnecessary use of device resources. Also make sure you put a Don't Touch attribute on the instantiated inverter before compiling your design. If you do not add this attribute, the inverter may get mapped into a CLB function generator. Most new synthesis tools automatically insert the STARTUP block and the previous steps are not required.
Note: For more information on simulating the Global Set/Reset, see the “Simulating Your Design” chapter.
Note: See the “Simulating Your Design” chapter for more information on STARTUP and STARTBUF.
The GSR pin on the STARTUP block or the GSRIN pin on the STARTBUF block drives the GSR net and connects to each flip-flop's Preset and Clear pin. When you connect a signal from a pad to the STARTUP block's GSR pin, the GSR net is activated. Because the GSR net is built into the silicon it does not appear in the pre-routed netlist file. When the GSR signal is asserted High (the default), all flip-flops and latches are set to the state they were in at the end of configuration. When you simulate the routed design, the gate simulator translation program correctly models the GSR function.
For the XC3000 family and the XC5200 family, all flip-flops and latches are reset to zero after configuration.
The XC4000 family flip-flops are configured as either preset (asynchronous set) or clear (asynchronous reset). Automatic assertion of the GSR net presets or clears each flip-flop. You can assert the GSR pin at any time to produce this global effect. You can also preset or clear individual flip-flops with the flip-flop's dedicated Preset or Clear pin. When a Preset or Clear pin on a flip-flop is connected to an active signal, the state of that signal controls the startup state of the flip-flop. For example, if you connect an active signal to the Preset pin, the flip-flop starts up in the preset state. If you do not connect the Clear or Preset pin, the default startup state is a clear state. To change the default to preset, assign an INIT=S attribute to the flip-flop.
I/O flip-flops and latches do not have individual Preset or Clear pins. The default value of these flip-flops and latches is clear. To change the default value to preset, assign an INIT=S attribute.
Refer to your synthesis tool documentation for information on changing the initial state of registers that do not use the Preset or Clear pins.
Many designs contain a net that initializes most of the flip-flops in the design. If this signal can initialize all the flip-flops, you can use the GSR/GR net. You should always include a net that initializes your design to a known state.
To ensure that your HDL simulation results at the RTL level match the synthesis results, write your code so that every flip-flop and latch is preset or cleared when the GSR signal is asserted. The synthesis tool cannot infer the GSR/GR net from HDL code. To utilize the GSR net, you must instantiate the STARTUP or STARTBUF block (VHDL), as shown in the “No_GSR Implemented with Gates” figure.
In the following VHDL and Verilog designs, the RESET signal initializes all the registers in the design; however, it does not use the dedicated global resources. The RESET signal is routed using regular routing resources. These designs include two 4-bit counters. One counter counts up and is reset to all zeros on assertion of RESET and the other counter counts down and is reset to all ones on assertion of RESET. The “No_GSR Implemented with Gates” figure shows the No_GSR design implemented with gates.
-- NO_GSR Example
-- The signal RESET initializes all registers
-- May 1997
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all
entity no_gsr is
port (CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
UPCNT: out STD_LOGIC_VECTOR (3 downto 0);
DNCNT: out STD_LOGIC_VECTOR (3 downto 0));
end no_gsr;
architecture SIMPLE of no_gsr is
signal UP_CNT: STD_LOGIC_VECTOR (3 downto 0);
signal DN_CNT: STD_LOGIC_VECTOR (3 downto 0);
begin
UP_COUNTER: process (CLOCK, RESET)
begin
if (RESET = '1') then
UP_CNT <= "0000";
elsif (CLOCK'event and CLOCK = '1') then
UP_CNT <= UP_CNT + 1;
end if;
end process;
DN_COUNTER: process (CLOCK, RESET)
begin
if (RESET = '1') then
DN_CNT <= "1111";
elsif (CLOCK'event and CLOCK = '1') then
DN_CNT <= DN_CNT - 1;
end if;
end process;
UPCNT <= UP_CNT;
DNCNT <= DN_CNT;
end SIMPLE;
-- NO_GR.VHD Example
-- The signal RESET initializes all registers
-- Without the use of the dedicated Global Reset
-- routing
-- December 1997
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity no_gr is
port (CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
UPCNT: out STD_LOGIC_VECTOR (3 downto 0);
DNCNT: out STD_LOGIC_VECTOR (3 downto 0));
end no_gr;
architecture XILINX of no_gr is
signal UP_CNT: STD_LOGIC_VECTOR (3 downto 0);
signal DN_CNT: STD_LOGIC_VECTOR (3 downto 0);
begin
UP_COUNTER: process (CLOCK, RESET)
begin
if (RESET = '1') then
UP_CNT <= "0000";
elsif (CLOCK'event and CLOCK = '1') then
UP_CNT <= UP_CNT + 1;
end if;
end process;
DN_COUNTER: process (CLOCK, RESET)
begin
if (RESET = '1') then
DN_CNT <= "1111";
elsif (CLOCK'event and CLOCK = '1') then
DN_CNT <= DN_CNT - 1;
end if;
end process;
UPCNT <= UP_CNT;
DNCNT <= DN_CNT;
end XILINX;
/* NO_GSR Example
* The signal RESET initializes all registers
* December 1997 */
module no_gsr ( CLOCK, RESET, UPCNT, DNCNT);
input CLOCK, RESET;
output [3:0] UPCNT;
output [3:0] DNCNT;
reg [3:0] UPCNT;
reg [3:0] DNCNT;
always @ (posedge CLOCK or posedge RESET) begin
if (RESET) begin
UPCNT = 4'b0000;
DNCNT = 4'b1111;
end else begin
UPCNT = UPCNT + 1'b1;
DNCNT = DNCNT - 1'b1;
end
end
endmodule
/* NO_GR.V Example
* The signal RESET initializes all registers
* Aug 1997 */
module no_gr ( CLOCK, RESET, UPCNT, DNCNT);
input CLOCK, RESET;
output [3:0] UPCNT;
output [3:0] DNCNT;
reg [3:0] UPCNT;
reg [3:0] DNCNT;
always @ (posedge CLOCK or posedge RESET) begin
if (RESET) begin
UPCNT = 4'b0000;
DNCNT = 4'b1111;
end else begin
UPCNT = UPCNT + 1'b1;
DNCNT = DNCNT - 1'b1;
end
end
endmodule
Figure 4.3 No_GSR Implemented with GatesTo reduce routing congestion and improve the overall performance of the reset net in the No_GSR and No_GR designs, use the dedicated GSR or GR net instead of the general purpose routing. Instantiate the STARTUP, STARTBUF, ROC, or TOC block in your design and use the GSR or GR pin on the STARTUP block (or the GSRIN pin on the STARTBUF block) to access the global reset net. This is not necessary with many synthesis tools. If you fully define the behavior of the GSR or GR net, the tool infers a STARTUP block. The modified designs (Use_GSR and Use_GR) are included at the end of this section. The Use_GSR design implemented with gates is shown in the “Active_Low_GSR Implemented with Gates” figure.
In XC4000 and Spartan designs, on assertion of the GSR net, flip-flops return to a clear (or Low) state by default. You can override this default by describing an asynchronous preset in your code, or by adding the INIT=”1” or equivalent attribute to the flip-flop (described later in this section).
In XC5200 family designs, the GR resets all flip-flops in the device to a logic zero. If a flip-flop is described as asynchronous preset to a logic 1, the synthesis tool automatically infers a flip-flop with a synchronous preset, and the Xilinx software puts an inverter on the input and output of the device to simulate a preset.
The Use_GSR and Use_GR designs explicitly state that the down-counter resets to all ones, therefore, asserting the reset net causes this counter to reset to a default of all zeros. You can use one of the following two methods to prevent this reset to zeros.
Xilinx recommends removing the comment characters from the last few lines of the Use_GSR or Use_GR code when you perform an RTL simulation and attaching the INIT=S attribute to the relevant flip-flops when you synthesize the design.
The STARTUP or STARTBUF block must not be optimized during the synthesis process. Add the appropriate attribute to prevent optimization before compiling your design.
-- USE_GSR.VHD Example
-- The signal RESET is connected to the
-- GSRIN pin of the STARTBUF block
-- May 1997
library IEEE;
library UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use UNISIM.all;
entity use_gsr is
port ( CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
UPCNT: out STD_LOGIC_VECTOR (3 downto 0);
DNCNT: out STD_LOGIC_VECTOR (3 downto 0));
end use_gsr;
architecture XILINX of use_gsr is
component STARTBUF
port (GSRIN: in STD_LOGIC);
GSROUT: out STD_LOGIC);
end component;
signal RESET_INT: STD_LOGIC;
signal UP_CNT: STD_LOGIC_VECTOR (3 downto 0);
signal DN_CNT: STD_LOGIC_VECTOR (3 downto 0);
begin
U1: STARTBUF port map(GSRIN=>RESET,
GSROUT=>RESET_INT);
UP_COUNTER: process(CLOCK, RESET_INT)
begin
if (RESET_INT = '1') then
UP_CNT <= "0000";
elsif CLOCK'event and CLOCK = '1') then
UP_CNT <= UP_CNT - 1;
end if;
end process;
DN_COUNTER: (CLOCK, RESET_INT)
begin
if (RESET_INT = '1') then
DN_CNT <= "1111";
elsif CLOCK'event and CLOCK = '1') then
DN_CNT <= DN_CNT - 1;
end if;
end process;
UPCNT <= UP_CNT;
DNCNT <= DN_CNT;
end XILINX;
------------------------------------------------
-- USE_GR.VHD Version 1.0 --
-- Xilinx HDL Synthesis Design Guide --
-- The signal RESET initializes all registers --
-- Using the global reset resources since --
-- STARTBUF block was added --
-- December 1997 --
------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use UNISIM.all;
entity use_gr is
port ( CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
UPCNT: out STD_LOGIC_VECTOR (3 downto 0);
DNCNT: out STD_LOGIC_VECTOR (3 downto 0));
end use_gr;
architecture XILINX of use_gr is
component STARTBUF
port (GSRIN: in STD_LOGIC;
GSROUT: out STD_LOGIC);
end component;
signal RESET_INT: STD_LOGIC;
signal UP_CNT: STD_LOGIC_VECTOR (3 downto 0);
signal DN_CNT: STD_LOGIC_VECTOR (3 downto 0);
begin
U1: STARTBUF port map(GSRIN=>RESET,
GSROUT=>RESET_INT);
UP_COUNTER: process(CLOCK, RESET_INT)
begin
if (RESET_INT = '1') then
UP_CNT <= "0000";
elsif (CLOCK'event and CLOCK = '1') then
UP_CNT <= UP_CNT + 1;
end if;
end process;
DN_COUNTER: process(CLOCK, RESET_INT)
begin
if (RESET_INT = '1') then
DN_CNT <= "1111";
elsif (CLOCK'event and CLOCK = '1') then
DN_CNT <= DN_CNT - 1;
end if;
end process;
UPCNT <= UP_CNT;
DNCNT <= DN_CNT;
end XILINX;
///////////////////////////////////////////////
// USE_GSR.V Version 1.0 //
// The signal RESET initializes all registers //
// Using the global reset resources (STARTUP) //
// December 1997 //
////////////////////////////////////////////////
module use_gsr ( CLOCK, RESET, UPCNT, DNCNT);
input CLOCK, RESET;
output [3:0] UPCNT;
output [3:0] DNCNT;
reg [3:0] UPCNT;
reg [3:0] DNCNT;
STARTUP U1 (.GSR(RESET));
always @ (posedge CLOCK or posedge RESET) begin
if (RESET) begin
UPCNT = 4'b0000;
DNCNT = 4'b1111;
end else begin
UPCNT = UPCNT + 1'b1;
DNCNT = DNCNT - 1'b1;
end
end
endmodule
///////////////////////////////////////////////
// USE_GR.V Version 1.0 //
// The signal RESET initializes all registers //
// Using the global reset resources since //
// STARTUP block instantiation was added //
// December 1997 //
////////////////////////////////////////////////
module use_gr ( CLOCK, RESET, UPCNT, DNCNT);
input CLOCK, RESET;
output [3:0] UPCNT;
output [3:0] DNCNT;
reg [3:0] UPCNT;
reg [3:0] DNCNT;
STARTUP U1 (.GR(RESET));
always @ (posedge CLOCK or posedge RESET) begin
if (RESET) begin
UPCNT = 4'b0000;
DNCNT = 4'b1111;
end else begin
UPCNT = UPCNT + 1'b1;
DNCNT = DNCNT - 1'b1;
end
end
endmodule
Figure 4.4 Active_Low_GSR Implemented with GatesThe Active_Low_GSR design is identical to the Use_GSR design except an INV is instantiated and connected between the RESET port and the STARTUP block. Also, a Set Don't Touch (or equivalent) attribute is added to the synthesis tool script for both the INV and STARTUP, or STARTBUF (VHDL) symbols. By instantiating the inverter, the global set/reset signal is now active low (logic level 0 resets all FPGA flip-flops). The inverter is absorbed into the STARTUP block in the device and no CLB resources are used to invert the signal. This is not necessary with many synthesis tools. If all registers and latches are described in the RTL code as reset or set, then a GSR or GR is inferred. Some tools also give you the option to select any signal as the GSR or GR net. This allows you to correct problems if the RTL code does not completely describe the GSR/GR behavior. However, the RTL code will not match the place and route behavior because not all registers are described as set or reset with the GSR/GR signal. Some tools provide a report of the inferred registers that are missing the GSR/GR behavior, and allow you to change the RTL behavior. VHDL and Verilog Active_Low_GSR designs are shown following.
----------------------------------------------------
-- ACTIVE_LOW_GSR.VHD Version 1.0 --
-- The signal RESET is inverted before being --
-- connected to the GSRIN pin of the STARTBUF --
-- The inverter will be absorbed by the STARTBUF --
-- September 1997 --
----------------------------------------------------
library IEEE;
library UNISIM;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use UNISIM.all;
entity active_low_gsr is
port ( CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
UPCNT: out STD_LOGIC_VECTOR (3 downto 0);
DNCNT: out STD_LOGIC_VECTOR (3 downto 0));
end active_low_gsr;
architecture XILINX of active_low_gsr is
component INV
port (I: in STD_LOGIC;
O: out STD_LOGIC);
end component;
component STARTBUF
port (GSRIN: in STD_LOGIC;
GSROUT: out STD_LOGIC);
end component;
signal RESET_NOT: STD_LOGIC;
signal RESET_NOT_INT: STD_LOGIC;
signal UP_CNT: STD_LOGIC_VECTOR (3 downto 0);
signal DN_CNT: STD_LOGIC_VECTOR (3 downto 0);
begin
U1: INV port map(I => RESET, O => RESET_NOT);
U2: STARTBUF port map(GSRIN=>RESET_NOT,
GSROUT=>RESET_NOT_INT);
UP_COUNTER: process(CLOCK, RESET_NOT_INT)
begin
if (RESET_NOT_INT = '1') then
UP_CNT <= "0000";
elsif (CLOCK'event and CLOCK = '1') then
UP_CNT <= UP_CNT + 1;
end if;
end process;
DN_COUNTER: process(CLOCK, RESET_NOT_INT)
begin
if (RESET_NOT_INT = '1') then
DN_CNT <= "1111";
elsif (CLOCK'event and CLOCK = '1') then
DN_CNT <= DN_CNT - 1;
end if;
end process;
UPCNT <= UP_CNT;
DNCNT <= DN_CNT;
end XILINX;
/////////////////////////////////////////////////////
// ACTIVE_LOW_GSR.V Version 1.0 //
// The signal RESET is inverted before being //
// connected to the GSR pin of the STARTUP bloc //
// The inverter will be absorbed by STARTUP in M1 //
// September 1997 //
//////////////////////////////////////////////////
module active_low_gsr ( CLOCK, RESET, UPCNT, DNCNT);
input CLOCK, RESET;
output [3:0] UPCNT;
output [3:0] DNCNT;
wire RESET_NOT;
reg [3:0] UPCNT;
reg [3:0] DNCNT;
INV U1 (.O(RESET_NOT), .I(RESET));
STARTUP U2 (.GSR(RESET_NOT));
always @ (posedge CLOCK or posedge RESET_NOT)
begin
if (RESET_NOT)
begin
UPCNT = 4'b0000;
DNCNT = 4'b1111;
end
else
begin
UPCNT = UPCNT + 1'b1;
DNCNT = DNCNT - 1'b1;
end
end
endmodule