Instantiating LogiBLOX Modules

Note: Refer to the LogiBLOX Guide for detailed instructions on using LogiBLOX.

Most synthesis tools can infer arithmetic modules from VHDL or Verilog code for these operators: +, -, <, <=, >, >=, =, +1, -1. These adders, subtracters, comparators, incrementers, and decrementers use FPGA dedicated device resources, such as carry logic, to improve the speed and area of designs. For bus widths greater than four, library modules are generally faster unless multiple instances of the same function are compiled together. For more information on the module libraries, refer to your synthesis tool documentation.

If you want to use a module that is not in the module libraries, you can use LogiBLOX to create components that can be instantiated in your code. This is useful for large memory arrays if your synthesis tool does not infer memory. However, Xilinx recommends properly constraining the synthesis and using the Xilinx-specific module generation capabilities of your tool. A simulation model is also created so that RTL simulation can be performed before your design is compiled.

You can create an instance of an externally defined macro, including a user-defined macro or a Xilinx macro (such as an I/O or flip-flop), by instantiating what some synthesis tool vendors refer to as a “black box” in your HDL code. These black boxes are Verilog empty module descriptions or VHDL component declarations.

Some synthesis tools allow instantiation of higher order Xilinx macros, such as counters and adders from the Unified library. Other synthesis tools provide Xilinx macro libraries that pre-define the Xilinx macros. Without this expansion, macros are not understood by the implementation tools. However, Xilinx does not recommend using these macros. The preferred method is the synthesis tool module expansion, or if you require more control, you can instantiate a LogiBLOX module. If necessary, use these macro libraries only with older schematic-based designs. However, even in these cases, schematic-based netlists are required to expand the macros, which makes the macro library redundant. LogiBLOX modules should also be unnecessary because the synthesis tool should provide equivalent performance. If you find a design in which this is not true, you can use LogiBLOX modules, and contact Xilinx and your synthesis vendor for a solution.

LogiBLOX is a graphical tool that allows you to select from several arithmetic, logic, I/O, sequential, and data storage modules for inclusion in your HDL design. Use LogiBLOX to instantiate the modules listed in the following table.

Table 4_2 LogiBLOX Modules

Using LogiBLOX in HDL Designs

1. Before using LogiBLOX, verify the following.
   
   
   • Xilinx software is correctly installed
     
     
   • Environment variables are set correctly
     
     
   • Your display environment variable is set to your machine's display
     
     
2. To run LogiBLOX, enter the following command.
   
   lbgui
   
   The LogiBLOX Setup Window appears after the LogiBLOX module generator is loaded. This window allows you to name and customize the module you want to create.
   
   
3. Select the Vendor tab in the Setup Window. Select your synthesis tool in the Vendor Name field to specify the correct bus notation for connecting your module.
   
   Select the Project Directory tab. Enter the directory location of your project in the LogiBLOX Project Directory field.
   
   Select the Device Family tab. Select the target device for your design in the Device Family field.
   
   Select the Options tab and select the applicable options for your design as follows.
   
   
   • Simulation Netlist
     
     This option allows you to create simulation netlists of the selected LogiBLOX module in different formats. You can choose one or more of the outputs listed in the following table.
     
     

     Table 4_3 Simulation Netlist Options

     Option	Description
     Behavioral VHDL netlist	Generates a simulation netlist in behavioral VHDL; output file has a .vhd extension.
     Gate level EDIF netlist	Generates a simulation netlist in EDIF format; output file has an .edn extension.
     Structural Verilog netlist	Generates a simulation netlist in structural Verilog; output file has a .v extension.

     
     
     
     
   • Component Declaration
     
     This option creates instantiation templates in different formats that can be copied into your design. You can select none, one, or both of the following options.
     
     

     Table 4_4 Component Declaration Options

     Option	Description
     VHDL template	Generates a LogiBLOX VHDL component declaration/instantiation template that is copied into your VHDL design when a LogiBLOX module is instantiated. The output file has a .vhi extension.
     Verilog template	Generates a LogiBLOX Verilog module definition/instantiation template that is copied into your Verilog design when a LogiBLOX module is instantiated. The output file has a .vei extension.

     
     
     
     
   • Implementation Netlist
     
     Select NGC File to generate an implementation netlist in Xilinx NGD binary format. You must select this option when instantiating LogiBLOX symbols in an HDL design. The output file has an .ngc extension and can be used as input to NGDBuild.
     
     
   • LogiBLOX DRC
     
     Select the Stop Process on Warning option to stop module processing if any warning messages are encountered during the design process.
     
     For example, if you have a Verilog design, and you are simulating with Verilog-XL, select Structural Verilog netlist, Verilog template, NGC File, and Stop Process on Warning. For a VHDL design and simulating with VSS, select Behavioral VHDL, VHDL template, NGC File, and Stop Process on Warning.
     
     Select OK.
     
     
4. Enter a name in the Module Name field in the Module Selector Window.
   
   Select a base module type from the Module Type field.
   
   Select a bus width from the Bus Width field.
   
   Customize your module by selecting pins and specifying attributes.
   
   After you have completed module specification, select OK.
   
   This initiates the generation of a component instantiation declaration, a behavioral model, and an implementation netlist.
   
   
5. Copy the module declaration/instantiation into your design. The template file created by LogiBLOX is module_name.vhi (VHDL) or module_name.vei (Verilog), and is saved in the project directory as specified in the LogiBLOX setup.
   
   
6. Complete the signal connections of the instantiated module to the rest of your design.
   
   

   Note: For more information on simulation, refer to the “Simulating Your Design” chapter.

7. Create an implementation script. Add the appropriate attribute to the instantiated LogiBLOX module to prevent synthesis of this module. Compile your design.
   
   Also, if you have a Verilog design, use a remove design type of command to make the LogiBLOX netlist unavailable before writing the .xnf or .edif netlist.
   
   

   Note: If you do not use a remove design type of command, the netlist file may be empty. If this occurs, the Xilinx software will trim this module/component and all connected logic. Refer to your synthesis tool documentation for the correct command and syntax.

8. Compile your design and create a .xnf or .edif file. You can safely ignore the following type of warning messages.
   
   Warning: Can't find the design in the library WORK. (LBR-1)
   
   Warning: Unable to resolve reference LogiBLOX_name in design_name. (LINK-5)
   
   Warning: Design design_name has 1 unresolved references. For more detailed information, use the “link” command. (UID-341)
   
   
9. Implement your design with the Xilinx tools. Verify that the .ngc file created by LogiBLOX is in the same project directory as the netlist.
   
   You may get the following warnings during the NGDBuild and mapping steps. These messages are issued if the Xilinx software can not locate the corresponding .ngc file created by LogiBLOX.
   
   Warning: basnu - logical block LogiBLOX_instance_name of type LogiBLOX_name is unexpanded. Logical Design DRC complete with 1 warning(s).
   
   If you get this message, you will get the following message during mapping.
   
   ERROR:basnu - logical block LogiBLOX_instance_name of type LogiBLOX_name is unexpanded. Errors detected in general drc.
   
   If you get these messages, first verify that the .ngc file created by LogiBLOX is in the project directory. If the file is there, verify that the module is properly instantiated in the code.
   
   
10. To simulate your post-layout design, convert your design to a timing netlist and use the back-annotation flow applicable to your synthesis tool.
    
    

    Note: For more information on simulation, refer to the “Simulating Your Design” chapter.

Instantiating a LogiBLOX “Black Box” Component

The VHDL example in this section shows how to instantiate a LogiBLOX “black box” component.

entity top is

    port (clk, rst, en, data: in bit; q: out bit);

end top;



architecture structural of top is

    -- Declare the black_box as a boolean attribute

    attribute black_box: boolean;

    -- Declare the black_box_pad_pin as a string attribute

    attribute black_box_pad_pin: string;



    -- In this example, GIZMO is a user macro that I created

    -- in a schematic editor, and

    -- that I want to directly instantiate in my VHDL design

    -- as a black box. Create a component declaration.

    component GIZMO

        port(Q: out bit; D, C, CLR: in bit);

    end component;

    -- Set the black_box attribute on GIZMO to be "true".

    attribute black_box of GIZMO:  component is true;



    -- In this example, MYBUF is a user I/O macro that I created

    -- in a schematic editor, and

    -- that I want to directly instantiate in my VHDL design

    -- as a black box. Create a component declaration.

    component MYBUF

        port(O: out bit; I: in bit);

    end component;

    -- Set the black_box_pad_pin attribute on MYBUF to 

    --   the pin that interfaces with the external world, "I".

    attribute black_box_pad_pin of MYBUF:  component is "I";



    signal data_core: bit;



begin

    -- Instantiate an MYBUF. Here we connect

    --    data to I and data_core to O.

    data_pad: MYBUF port map (O => data_core, I => data);



    -- Instantiate a GIZMO. Here we connect q to Q,

    --    data_core to D, clk to C, and rst to CLR.

    my_gizmo: GIZMO port map (Q => q, D => data_core, 

                C => clk, CLR => rst);

end structural;