Chapter 5

Simulating Your Design

This chapter describes simulation methods for verifying the functional timing of your designs. It includes the following sections.

• “Introduction”
  
  
• “Functional Simulation”
  
  
• “Timing Simulation”
  
  
• “Using VHDL/Verilog Libraries and Models”
  
  
• “Simulating Global Signals”
  
  
• “Adapting Schematic Global Signal Methodology for VHDL”
  
  
• “Setting VHDL Global Set/Reset Emulation in Functional Simulation”
  
  
• “Using Oscillators (VHDL)”
  
  
• “Compiling Verilog Libraries”
  
  
• “Setting Verilog Global Set/Reset”
  
  
• “Setting Verilog Global Tristate (XC4000, Spartan, and XC5200 Outputs Only)”