TRACE Options

This section describes the options to the TRACE command.

-a (Advanced Analysis)

The -a option can only be used if you are not supplying any timing constraints (in a PCF file) to TRACE. The -a option writes out a timing report containing the following.

• An analysis that enumerates all clocks and the required OFFSETs for each clock.
  
  
• An analysis of paths having only combinatorial logic, ordered by delay.
  
  

This information is supplied in place of the default information for the output timing report type (summary, error, or verbose).

If you want to perform an advanced analysis and you have timing constraints, then move the PCF file to another directory or rename the PCF file to a name other than the input design name. Remember to replace the PCF file when you are finished.

-dfs (Thorough timing analysis of paths)

The -dfs option specifies that TRACE utilize depth-first search timing analysis, which analyzes all paths covered by timing constraints in order to perform timing-driven place and route. This method is more thorough than the default method and may result in longer TRACE runtimes. See the -kpaths option for a discussion of the connection-based method.

-e (Generate an Error Report)

-e [limit]

The -e option generates an error report. The report has the same root name as the input design and a .twr extension. You can assign a different root name for the report on the command line, but the extension must be .twr.

The limit is an integer limit on the number of items reported per constraint. The integer limit can be used to limit the number of items reported for each timing constraint in the report file (the default is 3 items).

-f (Execute Commands File)

-f command_file

The -f option executes the command line arguments in the specified command_file. For more information on the -f option, see the “-f Option” section of the “Introduction” chapter.

-kpaths (Faster Analysis of Paths)

The non-enumerative connection-based method (the default) has a runtime proportional to the size of the design, unlike the DFS method, which has a runtime proportional to the number of paths in the design.

There are two significant differences between the connection-based method and the DFS method.

• The DFS method analyzes all paths except those that actually contain a circuit cycle, including paths that contain connections that cause a circuit cycle for other paths in the circuit. The connection-based method may not analyze these paths depending on circuit topology. The TRACE timing report contains a list of design connections that cause circuit cycles. The connection-based timing analysis may give more optimistic results for designs that have long paths with connections that cause circuit cycles.
  
  Consider the following example circuit.
  
  

  Figure 14.2 Circuit Cycles

  The DFS method traces the path from IN, through A, through the signal LOOP, back to the left-most logic block and to the signal OUT. The new connection-based method may not trace this path because a combinatorial cycle exists at the output of A.
  
  
• The DFS method removes false paths from a design that requires contending tristate enable signals. The connection-based method does not perform this optimization, which means that it may analyze some paths that are statically false based on tristate enable signals. The connection-based timing analysis may give more pessimistic results of designs that contain static false paths.
  
  Consider the following circuit.
  
  

  Figure 14.3 Tristate Buffer Paths

A signal can pass through four paths in the preceding circuit, but two of the paths are false (A1 to B2 and B1 to A2). In order for a signal to pass through the upper left tristate buffer A1, the enable signal A must be true. In order to prevent a bus contention on the A1 output, the enable signal B must be false. Since buffer B2 is also controlled by the enable signal B, the path through A1 cannot pass through B2 (because when A is enabled, B is disabled). The converse is also true, if B is enabled, the only valid path is from B1 to B2.

In the example circuit, the DFS method only considers true paths. The connection-based method will trace the false paths and the true paths.

-o (Output File Name)

-o outfile[.twr]

The -o option specifies the name of the output timing report. The .twr extension is optional.

-s (Change Speed)

-s [speed]

The -s option overrides the device speed contained in the input NCD file and instead performs an analysis for the device speed you specify. The -s option applies to whichever report type you produce in this TRACE run. The option allows you to see if faster or slower speed grades meet your timing requirements.

The device speed can be entered with or without the leading dash. For example, both -s 3 and -s -3 are valid entries.

Some architectures support minimum timing analysis. The command line syntax for min timing analysis is: trace -s min. Do not place a leading dash before min.

Note: The -s option only changes the speed grade for which the timing analysis is performed; it does not save the new speed grade to the NCD file.

-skew (Analyze Clock Skew for All Clocks)

-skew

This -skew option analyzes clock skew for all clocks including those using non-dedicated clock routing resources.

-stamp (Generates STAMP timing model files)

-stamp stampfile design.ncd

When you specify the -stamp option, TRACE generates a pair of STAMP timing model files stampfile.mod and stampfile.data that characterize the design's timing.

Note: A stampfile entry is required before the NCD file entry for the 2.1i release.

The STAMP compiler can be used for any board when performing static timing analysis.

There are four methods of running TRACE with the STAMP option to obtain a complete STAMP model report.

• Run with advanced analysis (-a)
  
  
• Run using default analysis (that is, with no constraint file and without advanced analysis).
  
  
• Construct constraints to cover all paths in the design.
  
  
• Run using the unconstrained path report (-u option) for constraints which only partially cover the design.
  
  

For either of the last two options, you should not have any path controls or TIGs or be aware that those paths are not part of the model.

-u (Report Uncovered Paths)

The -u option reports delays for paths that are not covered by timing constraints. The option adds an “Unconstrained path analysis” constraint to your existing constraints. This constraint performs a default path enumeration on any paths for which no other constraints apply. The default path enumeration includes circuit paths to data and clock pins on sequential components and data pins on primary outputs.

In the TRACE report, the following is included for the “Unconstrained path analysis” constraint.

• The minimum period for all of the uncovered paths to sequential components.
  
  
• The maximum delay for all of the uncovered paths containing only combinatorial logic.
  
  
• For a verbose report only, a listing of periods for sequential paths and delays for combinatorial paths. The list is ordered by delay in descending order, and the number of entries in the list can be controlled by specifying a limit when you enter the -v (Generate a Verbose Report) command line option.
  
  

-v (Generate a Verbose Report)

-v [limit]

The -v option generates a verbose report. The report has the same root name as the input design and a .twr extension. You can assign a different root name for the report on the command line, but the extension must be .twr.

The limit variable is an integer limit on the number of items reported per constraint. The integer limit can be used to limit the number of items reported for each timing constraint in the report file (the default is 3 items).