TRACE Output Details

Development System Reference GuideChapter 14: TRACE

TRACE Output Details

TRACE output is an ASCII timing report file that enables you to see how well the timing constraints for the design have been met. The file is written into your current working directory and has a .twr extension. The default name for the file is the same root name as the NCD file. You can designate a different root name for the file, but it must have a .twr extension. The extension .twr is assumed if not specified.

The timing report lists statistics on the design, any detected timing errors, and a number of warning conditions.

Timing errors indicate absolute or relative timing constraint violations. These include the following.

Path delay errors - where the path delay exceeds the maximum delay constraint for a path.
Net delay errors - where a net connection delay exceeds the maximum delay constraint for the net.
Offset errors - where either the delay offset between an external clock and its associated data-in pin is insufficient to meet the internal logic's timing requirements or the delay offset between an external clock and its associated data-out pin exceeds the external logic's timing requirements.
Net skew errors - where skew between net connections exceeds the maximum skew constraint for the net.

Timing errors may require design modifications, running PAR, or both.

Warnings point out potential problems such as circuit cycles or a constraint that does not define any paths.

Three types of reports are available. You determine the report type by entering the appropriate option entry on the UNIX or DOS command line or by selecting the type of report from the Timing Analyzer (see the “TRACE Options” section). Each type of report is described in the “Reporting with TRACE” section.

Timing Verification with TRACE

TRACE checks the delays in the NCD design file against your timing constraints. If delays are exceeded, TRACE issues the appropriate timing error.

Net Delay Constraints

The delay for a constrained net is checked to ensure that the constraint is equal to or greater than the routedelay.

constraint >= routedelay

routedelay is the signal delay between the driver pin and the load pin(s) on a net. This is an estimated delay if the design is placed but not routed.

Any nets showing delays that do not meet this condition generate timing errors in the timing report.

Net Skew Constraints

Signal skew on a net with multiple load pins is the difference between minimum and maximum load delays. Skew is checked against the specified maximum skew for constrained nets in the PCF file.

constraint >= (maxdelay - mindelay)

maxdelay is the maximum delay between the driver pin and a load pin.

mindelay is the minimum delay between the driver pin and a load pin.

If the skew is found to exceed the maximum skew constraint, the timing report shows a skew error.

Path Delay Constraints

The delay through a constrained path is checked to insure that the constraint is greater than or equal to the sum of logic (component) delay, route (wire) delay, and setup time (if any), minus clock skew (if any).

constraint >= logicdelay + routedelay + setuptime - clockskew

logicdelay is the pin-to-pin delay through a component.

routedelay is the signal delay between component pins in a path. This is an estimated delay if the design is placed but not routed.

setuptime (for clocked paths only) is the time that data must be present on an input pin before the arrival of the triggering edge of a clock signal.

clockskew (for register-to-register clocked paths only) is the difference between the amount of time the clock signal takes to reach the destination register and the amount of time the clock signal takes to reach the source register. Clock skew is discussed in the following section.

Paths showing delays that do not meet this condition generate timing errors in the timing report.

Clock Skew and Setup Checking

Clock skew must be accounted for in register-to-register setup checks. For register-to-register paths, the data delay must reach the destination register within a single clock period for the destination register. The timing analysis software ensures that any clock skew between the source and destination registers is accounted for in this check.

Note: In default mode, that is, without using the -skew option, only dedicated clock resource skew accounting is performed. With the
-skew option, non-dedicated clock skew accounting is also performed.

A setup check performed on register-to-register paths checks the following condition.

Slack = constraint + Tsk - (Tpath + Tsu)

constraint is the required time interval for the path, either specified explicitly by you with a FROM TO constraint, or derived from a PERIOD constraint.

Tpath is the summation of component and connection delays along the path (including the Tcko delay from the source register).

Tsu is the setup requirement for the destination register.

Tsk is the difference between the arrival time for the destination register and the source register.

Negative slack indicates that a setup error may occur, because the data from the source register does not set up at the target register for a subsequent clock edge.

In the following figure, the clock skew Tsk is the delay from the clock input (CLKIOB) to register D (TclkD) less the delay from the clock input (CLKIOB) to register S (TclkS). Negative skew relative to the destination reduces the amount of time available for the data path, and positive skew relative to the destination register is truncated to zero.

Figure 14.4 Clock Skew Example

Because the total clock path delay is used to determine the clock arrival times at the source register (TclkS) and the destination register (TclkD), this check still applies if the source and destination clocks originate at the same chip input but travel through different clock buffers and/or routing resources, as shown in the following figure.

Figure 14.5 Clock Passing Through Multiple Buffers

When the source and destination clocks originate at different chip inputs, no obvious relationship between the two clock inputs exists for the timing software (because the software cannot determine the clock arrival time or phase information).

For FROM TO specifications, the software assumes you have taken into account the external timing relationship between the chip inputs. The software assumes both clock inputs arrive simultaneously, and the difference between the destination clock arrival time (TclkD) and the source clock arrival time (TclkS) does not account for any difference in the arrival times at the two chip clock inputs.

Figure 14.6 Clocks Originating at Different Device Inputs

The clock skew Tsk is not accounted for in setup checks covered by PERIOD constraints where the clock paths to the source and destination registers originate at different clock inputs.

Reporting with TRACE

The timing report produced by TRACE is an ASCII file prepared for a particular design. It reports statistics on the design, a summary of timing warnings and errors, and optional detailed net and path delay reports.

Note: All TRACE reports are formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the reports uses a proportional font, the columns in the reports do not line up correctly.

This section covers the three different types of timing reports generated by TRACE. They are as follows.

The summary report - Contains summary information, design statistics, and statistics for each constraint in the PCF file.
The error report - Lists timing errors and associated net/path delay information.
The verbose report - Lists delay information for all nets and paths.

In each type of report, the header specifies the type of report, the input design name, the optional input physical constraints file name, and device and speed data for the input NCD file. At the end of each report is a timing summary, which includes the following information.

The number of timing errors found in the design. This information appears in all reports
A timing score, showing the total amount of error (in picoseconds) for all timing constraints in the design
The number of paths and nets covered by the constraints
The number of route delays and the percentage of connections covered by timing constraints

Note: The percentage of connections covered by timing constraints is given in a “% coverage” statistic. The statistic does not indicate the percentage of paths covered; it indicates the percentage of connections covered. Even if you have entered constraints that cover all paths in the design, this percentage may be less than 100%, since some connections are never included for static timing analysis (for example, connections to the STARTUP component).
The number of nets covered by constraints
A list of global statistics for the design

In the following sections, a description of each report is accompanied by a sample.

Following are some additional notes about timing reports.

For any of the three types of reports, if you specify a physical constraints file that contains invalid data, a list of physical constraints file errors appears at the beginning of the report. These include errors in constraint syntax.
In a TRACE report, a tilde (~) preceding a delay value indicates that the delay value is approximate. Values with the tilde cannot be calculated exactly because of excessive delays, resistance, or capacitance on the net, that is, the path is too complex too calculate accurately.

The tilde (~) also means that the path may exceed the numerical value listed next to the tilde by as much as 20%. You can use the PENALIZE TILDE constraint to penalize these delays by a specified percentage (see the “Attributes, Constraints, and Carry Logic” chapter of the Libraries Guide for a description of the PENALIZE TILDE constraint).
In a TRACE report, an “R” appended to a delay value indicates the value was calculated for a rising signal, and an “F” indicates the value for a falling signal. If rising and falling values are different, TRACE reports the appropriate delay.
TRACE detects when a path cycles (that is, when the path passes through a driving output more than once), and reports the total number of cycles detected in the design. When TRACE detects a cycle, it disables the cycle from being analyzed. If the cycle itself is made up of many possible routes, each route is disabled for all paths which converge through the cycle in question and the total number is included in the reported cycle tally.

A path is considered to cycle outside of the influence of other paths in the design. Thus if a valid path follows a cycle from another path, but actually converges at an input and not a driving output, the path is not disabled and will contain the elements of the cycle which may be disabled on another path.
In Xilinx FPGAs,455 tristate buffer (TBUF) outputs are always routed on longlines. Pullup resistors may also be tied to these longlines. The timing effects of a TBUF/pullup combination is handled differently in the various FPGA architectures.
- In XC3000A/L, XC3100A/L, 4000E/L, XC5200, and Spartan/XL designs, the delay associated with the longline is built into the component delay for the TBUF, and is not included in the delay reported for the net on the longline.
- In XC4000EX/XL/XV designs, the net delay on the longline is computed and reported as if the pullup (and not the TBUF output) is driving the net. If you want the delay to be computed with the TBUF driving the net, do not include any pullups at the output of the TBUF.

Error counts for both -dfs and -kpaths reflect the number of path endpoints (register setup inputs, output pads) that fail to meet timing specifications, not the number of paths that fail the specification. Consider the following circuit.

Figure 14.7 Error Reporting

If an error is generated at both the endpoints of A and B, the timing report would list two errors - one for each endpoint.

Data Sheet Reports

In 2.1i, the summary, error, and verbose reports contain a data sheet report. This report only includes IOs that are covered by the specified physical timing constraints, if any. A warning is issued if the report does not cover any IOs of the design due to the specified timing constraints. In the absence of a physical constraint file, all IO timing is analyzed and reported (less the effects of any default path tracing controls). Unconstrained path analysis can be used with a constraint file to increase the coverage of the report to include paths not explicitly specified in the constraints file. The report includes the source and destination PAD names, and either the propagation delay between the source and destination or the setup and hold requirements for the source relative to the destination. This report summarizes the following delay characteristics for the design:

External setup/hold requirements

The maximum setup and hold times of device data inputs are listed relative to each clock input. When two or more paths from a data input exist relative to a device clock input, the worst-case setup and hold times are reported. One worst-case setup and hold time is reported for each data input and clock input combination in the design.

Following is an example of an external setup/hold requirement in the data sheet report:
```
Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

start_i        |    2.816(R)|    0.000(R)|

---------------+------------+------------+
```

Clock-to-output propagation delays

The maximum propagation delay from clock inputs to device data outputs are listed for each clock input. When two or more paths from a clock input to a data output exist, the worst-case propagation delay is reported. One worst-case propagation delay is reported for each data output and clock input combination.

Following are two examples of clock-to-output propagation delays in the data sheet report:

Clock ck1_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out1_o         |   16.691(R)|

---------------+------------+

Clock to Setup on destination clock ck2_i

---------------+---------+---------+---------+------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+------+

ck2_i          |   12.647|         |         |      |

ck1_i          |   10.241|         |         |      |

---------------+---------+---------+---------+------+

Input-to-output propagation delays

The maximum propagation delay from each device input to each device output is reported if a combinational path exists between the device input and output. When two or more paths exist between a device input and output, the worst-case propagation delay is reported. One worst-case propagation delay is reported for every input and output combination in the design.

Following are examples of input-to-output propagation delays:

Pad to Pad

---------------+---------------+---------+

Source Pad     |Destination Pad|  Delay  |

---------------+---------------+---------+

BSLOT0         |D08            |   37.534|

BSLOT1         |D09            |   37.876|

BSLOT2         |D10            |   34.627|

BSLOT3         |D11            |   37.214|

CRESETN        |VCASN0         |   51.846|

CRESETN        |VCASN1         |   51.846|

CRESETN        |VCASN2         |   49.776|

CRESETN        |VCASN3         |   52.408|

CRESETN        |VCASN4         |   52.314|

CRESETN        |VCASN5         |   52.314|

CRESETN        |VCASN6         |   51.357|

CRESETN        |VCASN7         |   52.527|

---------------+---------------+----------

There are four methods of running TRACE to obtain a complete data sheet report.

Run with advanced analysis (-a)
Run using default analysis (that is, with no constraint file and without advanced analysis)
Construct constraints to cover all paths in the design
Run using the unconstrained path report for constraints which only partially cover the design

For either of the last two options, you should not have any path controls or TIGs or be aware that those paths will not be part of the report.

Guaranteed Setup and Hold Reporting

Guaranteed setup and hold values obtained from speed files are used in the data sheet reports for IOB input registers when these registers are clocked by specific clock routing resources and when the guaranteed setup and hold times are available for a specified device and speed.

Specific clock routing resources are clock networks that originate at a clock IOB, use a clock buffer to reach a clock routing resource and route directly to IOB registers.

Guaranteed setup and hold times are also used for reporting of input OFFSET constraints.

The following figure and text describes the external setup and hold time relationships.

Figure 14.8 Guaranteed Setup and Hold

The pad CLKPAD of clock input component CLKIOB drives a global clock buffer CLKBUF, which in turn drives an input flip-flop IFD. The input flip-flop IFD clocks a data input driven from DATAPAD within the component IOB.

Setup Times

The external setup time is defined as the setup time of DATAPAD within IOB relative to CLKPAD within CLKIOB. When a guaranteed external setup time exists in the speed files for a particular DATAPAD and the CLKPAD pair and configuration, this number is used in timing reports. When no guaranteed external setup time exists in the speed files for a particular DATAPAD and CLKPAD pair, the external setup time is reported as the maximum path delay from DATAPAD to the IFD plus the maximum IFD setup time, less the minimum of maximum path delay(s) from the CLKPAD to the IFD.

Hold Times

The external hold time is defined as the hold time of DATAPAD within IOB relative to CLKPAD within CLKIOB. When a guaranteed external hold time exists in the speed files for a particular DATAPAD and the CLKPAD pair and configuration, this number is used in timing reports.

When no guaranteed external hold time exists in the speed files for a particular DATAPAD and CLKPAD pair, the external hold time is reported as the maximum path delay from CLKPAD to the IFD plus the maximum IFD hold time, less the minimum of maximum path delay(s) from the DATAPAD to the IFD.

Summary Report

The summary report includes the name of the design file being analyzed, the device speed and report level, followed by a statistical brief that includes the summary information (timing errors, etc. described above) and design statistics. The report also list statistics for each constraint in the PCF file, including the number of timing errors for each constraint.

A summary report is produced when you do not enter an -e (error report) or -v (verbose report) option on the TRACE command line.

Two sample summary reports are shown below. The first sample shows the results without having a physical constraints file. The second sample shows the results when a physical constraints file is specified.

If no physical constraints file exists or if there are no timing constraints in the PCF file, TRACE performs default path and net enumeration to provide timing analysis statistics. Default path enumeration includes all circuit paths to data and clock pins on sequential components and all data pins on primary outputs. Default net enumeration includes all nets.

Note: The summary report is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

Summary Report (Without a Physical Constraints File Specified)

The following sample summary report represents the output of this TRACE command.

trce -o summary.twr testclk.ncd

The name of the report is summary.twr. No preference file is specified on the command line, and the directory containing the file testclk.ncd did not contain a PCF file called testclk.pcf.

-------------------------------------------------------------------------

Xilinx TRACE, Version 2.1i

Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.



-------------------------------------------------------------------------

Design file:              testclk.ncd

Physical constraint file: testclk.pcf

Device,speed:             xcv100,-5 (C 1.1.2.4 Advanced)

Report level:             summary report

-------------------------------------------------------------------------

WARNING:Timing - No timing constraints found, doing default enumeration.



Asterisk (*) preceding a constraint indicates it was not met.



---------------------------------------------------------------------

Constraint                                | Requested  | Actual     | Logic 

                                          |            |            |Levels

------------------------------------------------------------------------

Default period analysis                   |            | 13.321ns   | 12   

------------------------------------------------------------------------

Default net enumeration                   |            | 4.724ns    |      

-------------------------------------------------------------------------



All constraints were met.



Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)



Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

start_i        |    2.816(R)|    0.000(R)|

---------------+------------+------------+

Clock ck2_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out2_o         |   12.820(R)|

---------------+------------+





Clock ck1_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out1_o         |   15.086(R)|

---------------+------------+



Clock to Setup on destination clock ck2_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck2_i          |   12.647|         |         |         |

ck1_i          |   10.241|         |         |         |

---------------+---------+---------+---------+---------+



Clock to Setup on destination clock ck1_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck1_i          |   13.199|         |         |         |

---------------+---------+---------+---------+---------+

Timing summary:

---------------



Timing errors: 0  Score: 0



Constraints cover 2124 paths, 136 nets, and 380 connections (100.0% coverage)



Design statistics:

   Minimum period:  13.321ns (Maximum frequency:  75.069MHz)

   Maximum combinational path delay:  13.838ns

   Maximum net delay:   4.724ns





Analysis completed Mon Mar 29 07:17:41 1999

--------------------------------------------------------------

Summary Report (With a Physical Constraints File Specified)

The following sample summary report represents the output of this TRACE command.

trce -o summary1.twr testclk.ncd testclk.pcf

The name of the report is summary1.twr. The timing analysis represented in the file were performed by referring to the constraints in the file testclk.pcf.

-------------------------------------------------------------------------

Xilinx TRACE, Version 2.1i

Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.



Design file:              testclk.ncd

Physical constraint file: testclk.pcf

Device,speed:             xcv100,-5 (C 1.1.2.4 Advanced)

Report level:             summary report

-------------------------------------------------------------------------

Asterisk (*) preceding a constraint indicates it was not met.



------------------------------------------------------------------------

Constraint                                | Requested  | Actual     | Logic 

                                          |            |            |Levels

------------------------------------------------------------------------

TS_ck1_i = PERIOD TIMEGRP "ck1_i"  20 nS  | 20.000ns   | 13.321ns   | 12   

    HIGH 50.000 %                         |            |            |      

------------------------------------------------------------------------

TS_ck2_i = PERIOD TIMEGRP "ck2_i"  18 nS  | 18.000ns   | 12.653ns   | 11   

    HIGH 50.000 %                         |            |            |      

------------------------------------------------------------------------

OFFSET = IN 20 nS  BEFORE COMP "ck1_i"    | 20.000ns   | 2.816ns    | 2    

------------------------------------------------------------------------

OFFSET = OUT 18 nS  AFTER COMP "ck1_i"    | 18.000ns   | 15.086ns   | 5    

------------------------------------------------------------------------

OFFSET = IN 22 nS  BEFORE COMP "ck2_i"    |            |            |      

------------------------------------------------------------------------

OFFSET = OUT 17 nS  AFTER COMP "ck2_i"    | 17.000ns   | 12.820ns   | 5    

-------------------------------------------------------------------------



All constraints were met.





Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

start_i        |    2.816(R)|    0.000(R)|

---------------+------------+------------+



Clock ck2_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out2_o         |   12.820(R)|

---------------+------------+



Clock ck1_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out1_o         |   15.086(R)|

---------------+------------+



Clock to Setup on destination clock ck2_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck2_i          |   12.647|         |         |         |

ck1_i          |   10.241|         |         |         |

---------------+---------+---------+---------+---------+

Clock to Setup on destination clock ck1_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck1_i          |   13.199|         |         |         |

---------------+---------+---------+---------+---------+





Timing summary:

---------------



Timing errors: 0  Score: 0

Constraints cover 2124 paths, 0 nets, and 348 connections (91.6% coverage)



Design statistics:

   Minimum period:  13.321ns (Maximum frequency:  75.069MHz)

   Minimum input arrival time before clock:   2.816ns

   Minimum output required time after clock:  15.086ns





Analysis completed Mon Mar 29 07:00:11 1999

-------------------------------------------------------------------------

When the physical constraints file includes timing constraints, the summary report lists the percentage of all design connections covered by timing constraints. If there are no timing constraints, the report shows 100 percent coverage. An asterisk precedes constraints that fail.

Error Report

The error report lists timing errors and associated net/path delay information. Errors are ordered by constraint and, within constraints, by slack (the difference between the constraint and the analyzed value, with a negative slack indicating an error condition). The number of errors listed for each constraint is set by the limit you enter on the command line. The error report also contains a list of all time groups defined in the PCF file and all of the members defined within each group.

The main body of the error report lists all timing constraints as they appear in the input PCF file. If the constraint is met, the report simply states the number of items scored by TRACE, reports no timing errors detected, and issues a brief report line, indicating important information (for example, the maximum delay for the particular constraint). If the constraint is not met, it gives the number of items scored by TRACE, the number of errors encountered, and a detailed breakdown of the error.

For errors in which the path delays are broken down into individual net and component delays, the report lists each physical resource and the logical resource from which the physical resource was generated.

As in the other three types of reports, descriptive material appears at the top. A timing summary always appears at the end of the report. A sample error report follows.

Note: The error report is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

Sample Error Report

The following sample error report (error.twr) represents the output of this TRACE command.

trce -o error3.twr -e 3 test_clock.ncd

-------------------------------------------------------------------------

Xilinx TRACE, Version 2.1i

Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.



Design file:              testclk.ncd

Physical constraint file: testclk.pcf

Device,speed:             xcv100,-5 (C 1.1.2.4 Advanced)

Report level:             error report, limited to 3 items per constraint

-------------------------------------------------------------------------



=========================================================================

Timing constraint: TS_ck1_i = PERIOD TIMEGRP "ck1_i"  20 nS   HIGH 50.000 % ;

 955 items analyzed, 0 timing errors detected.

 Minimum period is  13.186ns.



.

.

.

========================================================================

Timing constraint: OFFSET = OUT 12 nS  AFTER COMP "ck1_i" ;

 12 items analyzed, 3 timing errors detected.

 Minimum allowable offset is  13.152ns.

Slack:    -1.152ns path ck1_i to out1_o relative to

           1.248ns delay ck1_i to core_inst1/counter1/regist0<0> and

          11.904ns delay core_inst1/counter1/regist0<0> to out1_o and

          12.000ns offset ck1_i to out1_o



Clock path ck1_i to core_inst1/counter1/regist0<0> contains 2 levels of

logic:

Path starting from Comp: Y11.PAD

To                   Delay type         Delay(ns)  Physical Resource

                                                   Logical Resource(s)

-------------------------------------------------  --------

Y11.GCLKOUT          Tgpid                 0.728R  ck1_i

                                                   ck1_i.PAD

                                                   C_ck1_i

GCLKBUF0.IN          net (fanout=1)        0.007R  N_ck1_i

GCLKBUF0.OUT         Tgio                  0.077R  BUFG_ck1

                                                   BUFG_ck1

CLB_R20C8.S0.CLK     net (fanout=16)       0.436R  ck1

-------------------------------------------------

Total (0.805ns logic, 0.443ns route)       1.248ns

      (64.5% logic, 35.5% route)



Data path core_inst1/counter1/regist0<0> to out1_o contains 5 levels of logic:

Path starting from Comp: CLB_R20C8.S0.CLK (from ck1)

To                   Delay type         Delay(ns)  Physical Resource

                                                   Logical Resource(s)

-------------------------------------------------  --------

CLB_R20C8.S0.XQ      Tcko                  1.147R  >

                                                   eg<0>

CLB_R19C8.S1.G1      net (fanout=4)        1.413R  >

CLB_R19C8.S1.Y       Tilo                  0.622R  syn2458

                                                   C386

CLB_R18C9.S0.G1      net (fanout=1)        1.237R  syn2458

CLB_R18C9.S0.Y       Tilo                  0.622R  out1

CLB_R18C9.S0.F3      net (fanout=1)        0.093R  syn632

CLB_R18C9.S0.X       Tilo                  0.622R  out1

                                                   C383

Y6.O                 net (fanout=11)       1.722R  out1

Y6.PAD               Tioop                 4.426R  out1_o

                                                   OBUF_out1

                                                   out1_o.PAD

-------------------------------------------------

Total (7.439ns logic, 4.465ns route)      11.904ns

      (62.5% logic, 37.5% route)



-------------------------------------------------------------------------

Slack:    -0.997ns path ck1_i to out1_o relative to

           1.248ns delay ck1_i to core_inst1/counter1/regist0<0> and

          11.749ns delay core_inst1/counter1/regist0<0> to out1_o and

          12.000ns offset ck1_i to out1_o

.

.

.

=========================================================================

Timing constraint: OFFSET = IN 22 nS  BEFORE COMP "ck2_i" ;

 0 items analyzed, 0 timing errors detected.

-------------------------------------------------------------------------

=========================================================================

Timing constraint: OFFSET = OUT 17 nS  AFTER COMP "ck2_i" ;

 12 items analyzed, 0 timing errors detected.

 Minimum allowable offset is  13.034ns.

-------------------------------------------------------------------------



1 constraint not met.





Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)



Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

start_i        |    2.957(R)|    0.000(R)|

---------------+------------+------------+

Clock ck2_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out2_o         |   13.034(R)|

---------------+------------+

.

.

.

Clock to Setup on destination clock ck1_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck1_i          |   13.186|         |         |         |

---------------+---------+---------+---------+---------+

Table of Timegroups:

-------------------

TimeGroup ck1_i:

BELs:

 core_inst1/counter1/regist1_reg<0>  core_inst1/counter1/regist1_reg<1>  st1/counter1/regist1_reg<2>  

 core_inst1/counter1/regist1_reg<3>  core_inst1/counter1/regist1_reg<4>  st1/counter1/regist1_reg<5> 

.

.

.



TimeGroup ck2_i:

BELs:

 core_inst2/counter1/regist1_reg<0>  core_inst2/counter1/regist1_reg<1>  st2/counter1/regist1_reg<2>  

 core_inst2/counter1/regist1_reg<3>  core_inst2/counter1/regist1_reg<4>  st2/counter1/regist1_reg<5>

.

.

.

core_inst2/counter1/cont_reg<7>     core_inst2/counter1/cont_reg<8>     st2/counter1/cont_reg<9>     

Timing summary:

---------------



Timing errors: 3  Score: 2457



Constraints cover 2124 paths, 0 nets, and 348 connections (91.6% coverage)



Design statistics:

   Minimum period:  13.186ns (Maximum frequency:  75.838MHz)

   Minimum input arrival time before clock:   2.957ns

   Minimum output required time after clock:  13.152ns





Analysis completed Tue Mar 30 07:40:08 1999

-------------------------------------------------------------------------

Verbose Report

The verbose report is similar to the error report, providing more details on delays for all constrained paths and nets in the design. Entries are ordered by constraint and, within constraints, by slack. The number of items listed for each constraint is set by the limit you enter on the command line.

Note: The data sheet report and STAMP model display skew values on non-dedicated clock resources that do not display in the default period analysis of the normal verbose report. The data sheet report and STAMP model must include skew because skew affects the external timing model. To display skew values in the verbose report, use the -skew option.

The verbose report also contains a list of all time groups defined in the PCF file, and all of the members defined within each group.

As in the other types of reports, descriptive material appears at the top.

The body of the verbose report enumerates each constraint as it appears in the input physical constraints file, the number of items scored by TRACE for that constraint, and the number of errors detected for the constraint. Each item is described, ordered by descending slack. A Report line for each item provides important information, such as the amount of delay on a net and by how much the constraint is met.

For path constraints, if there is an error, the report indicates the amount by which the constraint is exceeded. For errors in which the path delays are broken down into individual net and component delays, the report lists each physical resource and the logical resource from which the physical resource was generated.

If there are no errors, the report indicates that the constraint passed and by how much. Each logic and route delay is analyzed, totaled, and reported.

Note: The verbose report is formatted for viewing in a monospace (non-proportional) font. If the text editor you use for viewing the report uses a proportional font, the columns in the report do not line up correctly.

Sample Verbose Report

The following sample verbose report (verbose.twr) represents the output of this TRACE command.

trce -o verbose1.twr -v 1 testclk.ncd

-------------------------------------------------------------------------

Xilinx TRACE, Version 2.1i

Copyright (c) 1995-1999 Xilinx, Inc.  All rights reserved.



Design file:              testclk.ncd

Physical constraint file: testclk.pcf

Device,speed:             xcv100,-5 (C 1.1.2.4 Advanced)

Report level:             verbose report, limited to 1 item per constraint

-------------------------------------------------------------------------





=========================================================================

Timing constraint: TS_ck1_i = PERIOD TIMEGRP "ck1_i"  20 nS   HIGH 50.000 % ;

 955 items analyzed, 0 timing errors detected.

 Minimum period is  13.321ns.

-------------------------------------------------------------------------

Slack: 6.679ns path core_inst1/counter1/cont<1> to core_inst1/counter1/cont<9> relative to

          13.260ns delay constraint

           0.061ns clock skew

          20.000ns delay constraint

Path core_inst1/counter1/regist0<0> to core_inst1/counter1/cont<9> contains 12 levels of logic:

Path starting from Comp: CLB_R19C8.S1.CLK (from ck1)

To                   Delay type         Delay(ns)  Physical Resource

                                                   Logical Resource(s)

-------------------------------------------------  --------

CLB_R19C8.S0.YQ      Tcko                  1.147R  core_inst1/counter1/

                                                   /regist0<0>

                                                   core_inst1/counter1/

                                                   /regist0_reg<0>

CLB_R17C6.S1.XQ      net fanout=4)         2.422R  >

CLB_R17C6.S1.COUT    Topcyf                1.248R  O

                                                   C371

                                                   core_inst1/counter1/C9

                                                   /C2/C1

                                                   core_inst1/counter1/C9

                                                   /C3/C1

.

.

.

CLB_R17C5.S0.F3      net (fanout=1)        1.267R  core_inst1/counter1

                                                   /N362

CLB_R17C5.S0.CLK     Tick                  1.024R  core_inst1/counter1/

                                                   cont<9>

                                                   C303

                                                   core_inst1/counter1/

                                                   cont_reg<9>

-------------------------------------------------

Total (6.052ns logic, 7.208ns route)      13.260ns (to ck1)

      (45.6% logic, 54.7% route)

-------------------------------------------------------------------------

.

.

.

All constraints were met.





Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)



Setup/Hold to clock ck1_i

---------------+------------+------------+

               |  Setup to  |  Hold to   |

Source Pad     | clk (edge) | clk (edge) |

---------------+------------+------------+

start_i        |    2.816(R)|    0.000(R)|

---------------+------------+------------+



Clock ck2_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out2_o         |   12.820(R)|

---------------+------------+



Clock ck1_i to Pad

---------------+------------+

               | clk (edge) |

Destination Pad|   to PAD   |

---------------+------------+

out1_o         |   15.086(R)|

---------------+------------+



Clock to Setup on destination clock ck2_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck2_i          |   12.647|         |         |         |

ck1_i          |   10.241|         |         |         |

---------------+---------+---------+---------+---------+

Clock to Setup on destination clock ck1_i

---------------+---------+---------+---------+---------+

               | Src/Dest| Src/Dest| Src/Dest| Src/Dest|

Source Clock   |Rise/Rise|Fall/Rise|Rise/Fall|Fall/Fall|

---------------+---------+---------+---------+---------+

ck1_i          |   13.199|         |         |         |

---------------+---------+---------+---------+---------+





Table of Timegroups:

-------------------

TimeGroup ck1_i:

BELs:

 core_inst1/counter1/regist1_reg<0> core_inst1/counter1/regist1_reg<1>  >  

 core_inst1/counter1/regist1_reg<3> core_inst1/counter1/regist1_reg<4>  >  

 core_inst1/counter1/regist1_reg<6> core_inst1/counter1/regist1_reg<7>  >  

 core_inst1/counter1/regist1_reg<9> core_inst1/counter1/regist0_reg<0>  >  

 core_inst1/counter1/regist0_reg<2> core_inst1/counter1/regist0_reg<3>  >  

 core_inst1/counter1/regist0_reg<5> core_inst1/counter1/regist0_reg<6>  >  

 core_inst1/counter1/regist0_reg<8> core_inst1/counter1/regist0_reg<9>  core_inst1/counter1/cont_reg<0>     

 core_inst1/counter1/cont_reg<1>    core_inst1/counter1/cont_reg<2>     core_inst1/counter1/cont_reg<3>     

 core_inst1/counter1/cont_reg<4>    core_inst1/counter1/cont_reg<5>     core_inst1/counter1/cont_reg<6>     

 core_inst1/counter1/cont_reg<7>    core_inst1/counter1/cont_reg<8>     core_inst1/counter1/cont_reg<9>     





TimeGroup ck2_i:

BELs:

 core_inst2/counter1/regist1_reg<0> core_inst2/counter1/regist1_reg<1>  >  

 core_inst2/counter1/regist1_reg<3> core_inst2/counter1/regist1_reg<4>  >  

 core_inst2/counter1/regist1_reg<6> core_inst2/counter1/regist1_reg<7>  >  

 core_inst2/counter1/regist1_reg<9> core_inst2/counter1/regist0_reg<0>  >  

 core_inst2/counter1/regist0_reg<2> core_inst2/counter1/regist0_reg<3> 

core_inst2/counter1/regist0_reg<5>  core_inst2/counter1/regist0_reg<6>  >  

 core_inst2/counter1/regist0_reg<8> core_inst2/counter1/regist0_reg<9>  core_inst2/counter1/cont_reg<0>     

 core_inst2/counter1/cont_reg<1>    core_inst2/counter1/cont_reg<2>     core_inst2/counter1/cont_reg<3>     

 core_inst2/counter1/cont_reg<4>    core_inst2/counter1/cont_reg<5>     core_inst2/counter1/cont_reg<6>     

 core_inst2/counter1/cont_reg<7>    core_inst2/counter1/cont_reg<8>     core_inst2/counter1/cont_reg<9>     



Timing summary:

---------------



Timing errors: 0  Score: 0



Constraints cover 2124 paths, 0 nets, and 348 connections (91.6% coverage)



Design statistics:

   Minimum period:  13.321ns (Maximum frequency:  75.069MHz)

   Minimum input arrival time before clock:   2.816ns

   Minimum output required time after clock:  15.086ns

------------------------------------------------------------------------