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Following is a description of the flow types and how they affect the behavior of XFLOW. For a desired flow, select a combination of the
-implement, -tsim, -fit, -fsim, and -config flow types.
Note: The -fsim flow type must be used by itself and cannot be combined with the -implement, -tsim, -fit, or -config flow types.
You do not need to specify the complete path for option files on the command line. XFLOW searches for option files in the following hierarchy:
If you want to create your own option files, Xilinx recommends that you make a copy of an existing file, rename it option_file.opt, and then modify it.
-config option_file[.opt]
This flow type creates a bitstream for FPGA device configuration. The
-config flow type automatically invokes the fpga.flw flow file in the $XILINX/xilinx/data directory. The flow file runs only BITGEN.
Xilinx provides the bitgen.opt option file as the only option_file in the $XILINX/xilinx/data directory.
Note: The -config flow type requires a file name argument. There is no implied default.
Example:
The following example shows how to use a combination of flow types to implement and configure an FPGA.
xflow -p xcv100bg256-5 -implement balanced[.opt]
-config bitgen[.opt] testclk.edf
-fit option_file[.opt]
This flow type incorporates logic from a design into physical macrocell locations in a CPLD. Routing is performed automatically.
Xilinx provides three files as option_files in the $XILINX/epld/data directory. These files are shown in the following table.
| Option Files | Description |
|---|---|
| balanced.opt | balanced between speed and density |
| speed.opt | optimized for speed |
| density.opt | optimized for density |
The -fit flow type automatically copies the cpld.flw flow file from the $XILINX/epld/data directory. The flow file runs the ngdbuild, hitop, taengine, hprep sequence.
Note: The -fit flow type requires a file name argument. There is no implied default.
Example:
The following example shows how to use a combination of flow types to fit and perform a VHDL timing simulation on a CPLD.
xflow -p xc95144pq160-7 -fit balanced[.opt] -tsim generic_vhdl[.opt] main_pcb.edn
-fsim option_file[.opt]
This flow type performs a functional simulation for FPGA or CPLD designs.
Xilinx provides FPGA option_files in the $XILINX/xilinx/data directory and CPLD option_files in $XILINX/epld/data. The following table summarizes these option files.
| Flow Name | Family | Option File | Description |
|---|---|---|---|
VHDL Functional/Timing Simulation | FPGA/ CPLD | generic_vhdl.opt | Generic VHDL |
| active_vhdl.opt | Active VHDL | ||
| modelsim_vhdl.opt | Modelsim VHDL | ||
| vss_vhdl.opt | VSS VHDL | ||
| speedwave_vhdl.opt | Speedwave VHDL | ||
Verilog Functional/Timing Simulation | FPGA/ CPLD | generic_verilog.opt | Generic Verilog |
| modelsim_verilog.opt | Modelsim Verilog | ||
| concept_nc_verilog.opt | Concept-NC Verilog | ||
| concept_verilog_xl.opt | Concept Verilog-XL | ||
| nc_verilog.opt | NC Verilog | ||
| verilog_xl.opt | Verilog-XL | ||
| vcs_verilog.opt | VCS Verilog | ||
EDIF Functional/Timing Simulation Flow | FPGA/ CPLD | generic_edif.opt | Generic EDIF |
| fndtn_edif.opt | Foundation EDIF | ||
| viewsim_edif.opt | Viewsim EDIF | ||
| quicksim_edif.opt | Quicksim EDIF |
Note: The -fsim flow type requires a file name argument. There is no implied default. Also, you cannot use this flow type in conjunction with the -implement, -tsim, -config, or -fit flow types.
The following example show how to perform an EDIF functional simulation on an FPGA.
xflow -p xcv100bg256-5 -fsim generic_edif[.opt] testclk.edf
- implement option_file[.opt]
Xilinx provides three option_files in the $XILINX/xilinx/data directory. The -implement flow type automatically invokes the fpga.flw flow file in the $XILINX/xilinx/data directory. The flow file runs ngdbuild, map, trce, par, and trce.
Note: The -implement flow type requires a file name argument. There is no implied default.
The following table shows the option files provided by Xilinx.
| Option Files | Family | Description |
|---|---|---|
| fast_runtime.opt | FPGA | Runs the software tools non-timing driven. This option file provides the fastest runtimes at the expense of design performance. It is recommended for medium to slow speed designs. |
| balanced.opt | FPGA | Runs at PAR Effort Level 2. Operates at a level between fast_runtime.opt and high_effort.opt |
| high_effort.opt | FPGA | Runs the software tools timing driven at PAR Effort Level 4. High effort creates longer runtimes. It is recommended for creating designs that operate at high speeds. |
The following example show how to use the -implement flow type.
xflow -p xcv100bg256-5 -implement balanced[.opt] testclk.edf
XFLOW searches for the fpga.flw and balanced.opt files in the working directory. If these files cannot be found in the working directory, XFLOW copies the files to the working directory from either the path specified by the XFLOWPATH environment variable the install area and then executes the programs specified in the flow file. Note that you must have a file argument for the -implement flow type.
-tsim option_file[.opt]
This flow type performs a timing simulation for FPGA or CPLD designs.
Xilinx provides FPGA option_files in the $XILINX/xilinx/data directory and CPLD option_files in $XILINX/epld/data. See the “Option Simulation Files” table for a list of the files.
Note: The -tsim flow type requires a file name argument. There is no implied default.
Example:
The following example shows how to use a combination of flow types to fit and perform a VHDL timing simulation on a CPLD.
xflow -p xc95144pq160-7 -fit balanced.opt -tsim generic_vhdl.opt main_pcb.edn