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This appendix contains definitions and explanations for terms used in the FPGA Editor manual.
The Array window displays a graphical representation of the FPGA device. The device components and the interconnections (both logical and routed) between these components are displayed in this window. When you edit the internal logic of a programmable component such as a logic block, a schematic of the interior of the component is displayed in the Block window.
The automatic placement (AutoPlace) is software that selects sites intelligently based on routability. You can automatically place selected components in your design.
AutoRoute automatically routes the objects you specify.
A bank shot is a way of indirectly connecting two switch box pins that cannot be connected directly. If you want to route a bank shot through a switch box, you must select (in the correct order) the local lines leading to all of the pins you want to connect.
A group consisting of one or more logic functions.
The Block window is used to edit logic blocks. You can use only one Block window at a time for editing; however, you can have additional Block windows open for viewing.
An architecture feature of the Xilinx XC4000 and XC5200 families. Carry logic is designed to speed-up and reduce the area of counters, adders, incrementers, decrementers, comparators, and subtractors. It is a special interconnect that speeds up the carry path of adders and counters from one CLB to another. This dedicated carry line runs along each column of CLBs as well as the top and bottom CLBs. FPGA Express can synthesize carry logic directly.
The CLB, or Configurable Logic Block, constitutes the basic FPGA cell. It consists of two 16-bit function generators (F or G), one 8-bit function generator (H), two registers (flip-flops or latches), and reprogrammable routing controls (multiplexors).
Use the Command Line toolbar to enter commands from the keyboard.
A component is an instantiation of a physical logic cell such as a CLB or IOB.
Constraints are specifications for the implementation process. There are several categories of constraints: routing, timing, area, mapping, and placement constraints.
Using attributes, you can force the placement of logic (macros) in CLBs, the location of CLBs on the chip, and the maximum delay between flip-flops. PAR does not attempt to change the location of constrained logic.
CLBs are arranged in columns and rows on the FPGA device. The goal is to place logic in columns on the device to attain the best possible placement from the point of view of performance and space.
A constraints file specifies constraints (location and path delay) information in a textual form. You can also place constraints on a schematic.
This tool calculates and displays the delay associated with load pins and driver pins in a given net or path.
Physical DRC is a series of tests to discover physical errors and some logic errors in your design.
A device is an integrated circuit or other solid-state circuit formed in semiconducting materials during manufacturing.
A macro pin used to connect the components in an instantiated macro to other components in your design (outside of the macro).
An FPGA, or field programmable gate array, is a class of integrated circuits pioneered by Xilinx for which the logic function is defined by the customer using Xilinx development system software after the IC has been manufactured and delivered to the end user.
A graphical application for displaying and configuring Field Programmable Gate Arrays (FPGAs).
Script that determines what FPGA Editor commands are performed when the FPGA Editor starts up.
You can customize the fpga_editor.ini initialization file by creating an fpga_editor_user.ini file in your home directory. When the FPGA Editor is initialized, it reads the fpga_editor.ini file first and then the fpga_editor_user.ini file.
The History toolbar is located below the Array window and displays commands and responses. All error messages, warnings, and command responses are written to the History toolbar. Information in the History toolbar is especially useful for deciphering unexpected command results.
An IOB is a collection or grouping of basic elements that implement the input and output functions of an FPGA device.
An FPGA Editor layer contains all of one type of object (for example, all long lines in the device, or all components in the design database).
The Layer Visibility toolbar allows you to specify which objects are displayed in the Array window. Select the layers you want displayed and deselect the layers you want hidden.
The List window displays a list of the components, nets, layers, paths, and macros in your design. Use the pull-down list box at the top of the window to specify the items you want displayed in the List window.
Local lines usually span across multiple CLBs; typically they are between switch boxes. Local lines do not directly connect to site pins, such as direct connects, and they do not span across the entire length of the device, such as long lines.
Lock placement applies a constraint to all placed components in your design. This option specifies that placed components cannot be unplaced, moved, or deleted.
The log file is a command log file. This file records all FPGA Editor commands executed and output generated.
A long line connects to a primary global net or to any secondary global net. Each CLB has four dedicated vertical longlines. These lines are very fast. Long lines usually span the entire width or height of the device.
A look-up table, or LUT, implements Boolean functions.
See the “physical macros” section.
A copy of a macro library file inserted in a design file. When you add a macro instance to a design you “instantiate” the macro. A design may contain multiple instances of the same library file, and each will receive a unique name. Since the library file is copied into the design file when you instantiate a macro, if you then change the library file the changes will not be reflected in the macro instantiated in the design file. In this User's Guide, the word “macro” may be used instead of “macro instance.” A macro library file will always be referred to as a “macro library file.”
A file containing the definition of a macro. Macro library files have an .nmc extension.
The menu bar is located above the Array window. Most of the FPGA Editor commands are available in the pull-down menus of the FPGA Editor window after a design is loaded.
Mapping is the process of assigning a design's logic elements to the specific physical elements that actually implement logic functions in a device.
A NCD file is the output design file from the MAP program and represents the physical design.
1. A net is a logical connection between two or more symbol instance pins. After routing, the abstract concept of a net is transformed to a physical connection called a wire.
2. A net is an electronic connection between components or nets. It can also be a connection from a single component. It is the same as a wire or a signal.
Displays the delay for all pins in a net. You can either find the delay for all pins in the net or you find delays for specific pins.
A NMC file contains a physical macro which can be created or viewed with the FPGA Editor.
A package is the physical packaging of a chip, for example, PG84, VQ100, and PC48.
A path is a connected series of nets and logic elements. A path has a start point and an end point that are different depending on the type of path. The time taken for a signal to propagate through a path is referred to as the path delay.
A path delay is the time taken for a signal to propagate through a path.
The PCF file is an ASCII file containing physical constraints created by the MAP program as well as physical constraints entered by you. You can edit the PCF file in the FPGA Editor.
Physical Design Rule Check (DRC) is a series of tests to discover logical and physical errors in the design. Physical DRC is applied to the FPGA Editor and BITGEN. Results of the DRC are written into the history area.
A physical macro is a logical function that has been created from components of a specific device family. Physical macros are stored in files with the extension .nmc.
A pin is an attachment point on a site or a component. Nets can be attached to pins.
Pinwires are wires which are directly tied to the pin of a site (i.e. CLB, IOB, etc.)
Placing is the process of assigning physical device cell locations to the logic in a design.
Properties are instructions placed on symbols or nets in an FPGA or CPLD schematic to indicate their placement, implementation, naming, directionality, or other properties.
A ratsnest consists of lines that are point to point connections between unrouted pins on a given net.
A component in the macro library file used as a reference when a macro instance is placed, moved, or copied. Placement and routing of all other pre-placed macro components are determined relative to this component.
The router is the utility that connects all appropriate pins to create the design's nets.
The process of assigning logical nets to physical wire segments in the FPGA that interconnect logic cells.
A route that can pass through an occupied or an unoccupied CLB site is called a route-through. You can manually do a route-through in the FPGA Editor. Route-throughs provide you with routing resources that would otherwise be unavailable.
A site is a programmable logic element (used or unused) location within the device, sites are potential locations for components and are displayed in the Array window as outlines of components.
Speed is a function of net types, CLB density, switching matrices, and architecture.
The status bar appears at the bottom of the main window. When you select a menu command, a brief description of the command's function appears in the status bar.
A switch matrix is a collection of transistors located between CLB blocks that enables the connection of two interconnect lines. PPR uses the switch matrices and interconnects to connect CLB inputs and outputs. Switch matrices reduce some of the net delay. They have three possible directions: top, bottom, and left.
The title bar displays the program name and the name of the currently loaded design.
Timing is the process that calculates the delays associated with each of the routed nets in the design.
TRACE (Timing Reporter and Circuit Evaluator) is a program you can run within the FPGA Editor that provides static timing analysis of the physical design based on input timing constraints.
The User toolbar provides a convenient way to perform frequently used commands. To use a command, select the appropriate command button with the left mouse button.
A wire is a net or a signal. See the “net” section.
The World window shows the area of the device that is currently displayed in the Array window. As you pan and zoom the Array window, notice the corresponding changes in the size and position of the rectangle within the World window. Also, any objects selected in the Array window appear in the World window. You can drag the inner box with the mouse button to pan the display to the desired position. If you have multiple Array windows, the World window displays a rectangle for each Array window.