Constraints

FPGA Editor GuideChapter 3: Using the FPGA Editor

Constraints

You can add certain constraints to or delete certain constraints from the .pcf file in the FPGA Editor. In the FPGA Editor, net, site, and component constraints are supported as property fields in the individual nets and components. Properties are set with the Setattr command and are read with the Getattr command. All Boolean constraints (block, locate, lock, offset, and prohibit) have values of On or Off; offset direction has a value of either In or Out; and offset order has a value of either Before or After. All other constraints have a numeric value and can also be set to Off to delete the constraint. All values are case-insensitive (for example, “On” and “on” are both accepted).

When you create a constraint in the FPGA Editor, the constraint is written to the PCF file whenever you save your design. When you use the FPGA Editor to delete a constraint and then save your design file, the line on which the constraint appears in the PCF file remains in the file but it is automatically commented out.

Some of the constraints supported in the FPGA Editor are listed in the following table.

Table 3_4 Constraints

Constraint	Accessed Through
block paths	Component Properties and Path Properties property sheet
define path	Created, edited, and removed with Add and Delete; viewed with Path Properties property sheet
location range	Component Properties Constraints page
locate macro	Macro Properties Constraints page
lock placement	Component Properties Constraints page
lock macro	Macro Properties Constraints page
lock routing of this net	Net Properties Constraints page
lock placement	Component Properties Constraints page
lock routing	Net Properties Constraints page
maxdelay allnets	Main Properties Constraints page
maxdelay allpaths	Main Properties Constraints page
maxdelay net	Net Properties Constraints page
maxdelay path	Path Properties property sheet
maxskew	Main Properties Constraints page
maxskew net	Net Properties Constraints page
offset comp	Component Properties Offset page
penalize tilde	Main Properties Constraints page
period	Main Properties Constraints page
period net	Net Properties Constraints page
prioritize net	Net Properties Constraints page
prohibit site	Site Properties property sheet

All constraints properties can also be set with property sheets. Properties and corresponding constraints are listed in the following tables.

Main Properties	Constraint
penalize_tilde	penalize tilde
allnets_maxdelay	maxdelay allnets
allpaths_maxdelay	maxdelay allpaths
clknets_period	period
clknets_maxskew	maxskew

Component Properties	Constraint
lock	lock comp
locate	locate comp
offset	offset comp
offset_comp1	Argument to offset comp
offset_comp2	Argument to offset comp
offset_order	Argument to offset comp
offset_direction	Argument to offset comp
offset_time	Argument to offset comp
block	block comp

Net Properties	Constraint
lock	lock net
block	block net
prioritize	prioritize net
maxdelay	maxdelay net
maxskew	maxskew net
period	period net

Macro Properties	Constraint
locate	locate macro
lock	lock macro

Path Properties	Constraint
block	block path
maxdelay	maxdelay path

Site Properties	Constraint
prohibit	prohibit site

Locked Nets and Components

If a net is locked, you cannot unroute any portion of the net, including the entire net, a net segment, a pin, or a wire. To unroute the net, you must first unlock it. You can add pins or routing to a locked net.

A net is displayed as locked in the FPGA Editor if the Lock Net [net_name] constraint is enabled in the PCF file. You can use the Net Properties property sheet to remove the lock constraint.

When a component is locked, one of the following constraints is set in the PCF file.

lock comp [comp_name]
locate comp [comp_name]
lock macro [macro_name]
lock placement

If a component is locked, you cannot unplace it, but you can unroute it. To unplace the component, you must first unlock it.