Adding Probes to Your Design

You can add probes to your design to examine the signal states of the targeted FPGA device, as described in the following procedure.

Adding a Probe

1. Select Tools Probes to display the Probes dialog box, as shown in the “Probes Dialog Box” figure of the “Menu Commands” chapter.
   
   
2. Select Add to display the dialog box shown in the “Define Probe Dialog Box” figure of the “Menu Commands” chapter.
   
   
3. Fill in the fields in this dialog box to define the probe. See the “Define Probe Dialog Box Options” section of the “Menu Commands” chapter for the definitions of the fields
   
   
4. Select OK to close the dialog box.
   
   The probe is automatically routed, and the defined probe is displayed in the Probes dialog box.
   
   
5. Select the BitGen option in the Probes dialog box to display the dialog box shown in the “Run BitGen Dialog Box” figure of the “Menu Commands” chapter.
   
   
6. The file name displayed in the Bit File Name field is the name of your probed design. If you change the name to design_name.bit, you are warned that this name represents your unprobed design. You can select Yes to save the bit file under this name or No to save the bit file under the name provided by the system.
   
   
7. Click OK to return to the Probes dialog box.
   
   
8. Select Download to start the Hardware Debugger tool so you can download your bit file to a test device. This tool is run in a separate process from the FPGA Editor.