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| XC3000 | XC4000E | XC4000X | XC5200 | XC9000 | Spartan | SpartanXL | Spartan2 | Virtex |
|---|---|---|---|---|---|---|---|---|
| N/A | Primitive | Primitive | N/A | N/A | Primitive | Primitive | Macro | Macro |
ILDXI_1 is a transparent data latch, which can hold transient data entering a chip. When the gate input (G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High G transition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied. FPGAs simulate power-on when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP, STARTUP_SPARTAN2, or STARTUP_VIRTEX symbol.
For information on legal IFDXI, IFDXI_1, ILDXI, and ILDXI_1 combinations, refer to the “ILDXI” section.
| Inputs | Outputs | ||
|---|---|---|---|
| GE | G | D | Q |
| 0 | X | X | No Chg |
| 1 | 1 | X | No Chg |
| 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 |  | D | d |
| d = state of referenced input one setup time prior to Low-to-High gate transition | |||
Figure 6.43 ILDXI_1 Implementation Spartan2, Virtex