Evaluating Design Size and Performance

Synthesis and Simulation Design GuideChapter 3: Understanding High-Density Design Flow

Evaluating Design Size and Performance

Your design should meet the following requirements.

Design must function at the specified speed
Design must fit in the targeted device

After your design is compiled, you can determine preliminary device utilization and performance with your synthesis tool's reporting options. After your design is mapped by the Xilinx tools, you can determine the actual device utilization. At this point in the design flow, you should verify that your chosen device is large enough to incorporate any future changes or additions, and that your design will perform as specified.

Using your Synthesis Tool to Estimate Device Utilization and Performance

Use your synthesis tool's area and timing reporting options to estimate device utilization and performance. After compiling, use the report area command to obtain a report of device resource utilization. Some synthesis tools provide area reports automatically. Refer to your synthesis tool documentation for correct command syntax.

Note: See the “Report Files” appendix for sample report files from various synthesis vendors.

This report lists the compiled cells in your design, as well as information on how your design is mapped in the FPGA. These reports are generally accurate for the XC4000 and Spartan family because the synthesis tool creates the logic from your code and maps your design into the FPGA. However, these reports are different for the various synthesis tools. Some reports specify the minimum number of CLBs required, while other reports specify the “unpacked” number of CLBs to make an allowance for routing. For an accurate comparison, you should compare reports from the Xilinx place and route tool after implementation. Also, any instantiated components, such as LogiBLOX modules, EDIF files, XNF files, or other components that your synthesis tool does not recognize during compilation are not included in the report file. If you include these components in your design, you must include the logic area used by these components when estimating design size. Also, sections of your design may get trimmed during the mapping process, and may result in a smaller design.

Using the Timing Report Command

Use your synthesis tool's timing report command to obtain a report with estimated data path delays. Refer to your synthesis vendor's documentation for command syntax.

Note: See the “Report Files” appendix for sample report files from various synthesis vendors.

This report is based on the logic level delays from the cell libraries and estimated wire-load models for your design. This report is an estimate of how close you are to your timing goals; however, it is not the actual timing for your design. An accurate report of your design's timing is only available after your design is placed and routed. This timing report does not include information on any instantiated components, such as LogiBLOX modules, EDIF files, XNF files, or other components that are not recognized by your synthesis tool during compilation.

Determining Actual Device Utilization and Pre-routed Performance

To determine if your design fits the specified device, you must map it with the Xilinx Map program. The generated report file design_name.mrp contains the implemented device utilization information. You can run the Map program from the Design Manager or from the command line.

Using the Design Manager to Map Your Design

Use the following steps to map your design using the Design Manager.

Note: For more information on using the Design Manager, see the Design Manager/Flow Engine Reference/User Guide.

To start the Design Manager, enter the following command.

xilinx
To create a new project, select the XNF or EDIF file generated by your synthesis tool as your input file from the File New Project menu command.
To start design implementation, click the Implement toolbar button or select Design Implement.

The Implement dialog box appears.
If necessary, select a part in the dialog box.
Select the Options button in the Implement dialog box.

The Options dialog box appears.
Select the Produce Logic Level Timing Report option.

This option creates a timing report prior to place and route, but after map, as described in the following five steps.
Select the Edit Template button next to the Implementation drop-down list.

The Implementation Template dialog box appears.
Select the Timing tab.
Select the Produce Logic Level Timing Report radio button.
Select the type of report you want to create.

The default is Report Paths in Timing Constraints.
Use the Implementation Template dialog box tabs (Optimize & Map, Place & Route, or Interface) to select any other options applicable to your design. Select OK to exit the Implementation Template dialog box.

Note: Xilinx recommends using the default Map options for your designs. Also, do not use the guided map option with your synthesized designs.
Select Run in the Implement dialog box to begin implementing your design.
When the Flow Engine is displayed, stop the processing of your design after mapping by selecting Setup Stop After or by selecting the Set Target toolbar button.

The Stop After dialog box appears.
Select Map and select OK.
After the Flow Engine is finished mapping your design, select Utilities Report Browser to view the map report. Double-click the report icon that you want to view. The map report includes a Design Summary section that contains the device utilization information.
View the Logic Level Timing Report with the Report Browser. This report shows the performance of your design based on logic levels and best-case routing delays.
At this point, you may want to start the Timing Analyzer from the Design Manager to create a more specific report of design paths.
Use the Logic Level Timing Report and any reports generated with the Timing Analyzer or the Map program to evaluate how close you are to your performance and utilization goals. Use these reports to decide whether to proceed to the place and route phase of implementation, or to go back and modify your design or implementation options to attain your performance goals. You should have some slack in routing delays to allow the place and route tools to successfully complete your design. Use the verbose option in the Timing Analyzer to see block-by-block delay. The timing report of a mapped design (before place and route) shows block delays, as well as estimated routing delays.

Using the Command Line to Map Your Design

Translate your design as follows.

ngdbuild -p target_device design_name.xnf
Map your design as follows.

map design_name.ngd
Use a text editor to view the Device Summary section of the design_name.mrp map report. This section contains the device utilization information.
Run a timing analysis of the logic level delays from your mapped design as follows.

trce [options] design_name.ngd

Note: For available options, enter only the trce command at the command line without any arguments.
Use the Trace reports to evaluate how close you are to your performance goals. Use the report to decide whether to proceed to the place and route phase of implementation, or to go back and modify your design or implementation options to attain your performance goals. You should have some slack in routing delays to allow the place and route tools to successfully complete your design.

The following is the Device Summary section of a Map report.

Design Summary

--------------

   Number of errors:        0

   Number of warnings:      3

   Number of CLBs:             39 out of   100   39%

      CLB Flip Flops:      32

      4 input LUTs:        66

      3 input LUTs:         5

   Number of bonded IOBs:      30 out of    61   49%

      IOB Flops:            0

      IOB Latches:          0

   Number of secondary CLKs:    1 out of     4   25%

   Number of oscillators:       1

   Number of STARTUPs:          1

   Number of READCLKs:          1

   Number of READBACKs:         1

   Number of MD0 pads:          1

   Number of MD1 pads:          1

Total equivalent gate count for design: 1538

Additional JTAG gate count for IOBs:    1536

The following is a sample Logic Level Timing Report.

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Xilinx TRACE, Version M1.4.12

Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.



Design file:              map.ncd

Physical constraint file: demo_board.pcf

Device,speed:             xc4003e,-2 (x1_0.86  PRELIMINARY)

Report level:             summary report

-------------------------------------------------------------------------



=========================================================================

Timing constraint: NET "FAST_CLOCK" PERIOD =  15.200 nS   HIGH 50.000 % ;

 1 item analyzed, 0 timing errors detected.

 Minimum period is   5.585ns.

-------------------------------------------------------------------------



=========================================================================

Timing constraint: NET "control_logic/SLOW_CLOCK" PERIOD =  121.600 nS   HIGH 50.000 % ;

 677 items analyzed, 0 timing errors detected.

 Minimum period is  17.295ns.

-------------------------------------------------------------------------



All constraints were met.



Timing summary:

---------------



Timing errors: 0  Score: 0



Constraints cover 811 paths, 0 nets, and 232 connections (73.2% coverage)



Design statistics:

   Minimum period:  17.295ns (Maximum frequency:  57.820MHz)



Analysis completed Tue Jan 27 12:07:59 1998

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