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For Verilog simulation, all behaviorally described (inferred) and instantiated registers should have a common signal which asynchronously sets or resets the register. You must toggle the global set/reset signal (GSR for XC4000E/L/X, Spartan/XL, and Virtex designs, or GR for XC5200, XC3000A/L, or XC3100A/L designs). Toggling the global set/reset emulates the Power-On-Reset of the FPGA. If you do not do this, the flip-flops and latches in your simulation enter an unknown state.
The GSR signal in XC4000E/L/X, Spartan/XL, and Virtex devices, and the GR signal in XC5200 devices are active High. The GR signal in XC3000A/L and XC3100A/L devices are active Low.
The global set/reset net is present in your implemented design even if you do not instantiate the STARTUP block in your design. The function of STARTUP is to give you the option to control the global reset net from an external pin.
If you want to set the global set/reset pulse width so that it reflects the actual amount of time it takes for the chip to go through the reset process when power is supplied to it, refer to The Programmable Logic Data Book for the device you are simulating. The duration of the pulse is specified as TPOR (Power-On-Reset).
The general procedure for specifying global set/reset or global reset during a pre-NGDBuild Verilog UniSims simulation involves defining the global reset signals with the $XILINX/verilog/src/glbl.v module. The VHDL UniSims library contains the ROC, ROCBUF, TOC, TOCBUF, and STARTBUF cells to assist in VITAL VHDL simulation of the global set/reset and tri-state signals. However, Verilog allows a global signal to be modeled as a wire in a global module, and, thus, does not contain these cells.
Note: In the Xilinx software, the Verilog UniSims library is only used in RTL simulations of your designs. Simulation at other points in the flow use the Verilog SimPrims Libraries.
For pre-NGDBuild UniSims functional simulation, you must set the value of the appropriate Verilog global signals (glbl.GSR or glbl.GR) to the name of the GSR or GR net, qualified by the appropriate scope identifiers.
The scope identifiers are a combination of the test module scope and the design instance scope. The scope qualifiers are required because the scope information is needed when the glbl.GSR and glbl.GR wires are interpreted by the Verilog UniSims simulation models to emulate a global reset signal.
For post-NGDBuild and post-route timing simulation, the testfixture template (.tv file) produced by running NGD2VER with the -tf option contains most of the code previously described for defining and toggling GSR or GR.
Use the following steps to define the global set/reset signals in a testfixture for your design.
Note: In the following steps, testfixture_name refers to the test fixture module name and instance_name refers to the designated instance name for the instantiated design netlist within the test bench.
Note: Xilinx recommends giving the name test to the main module in the test fixture file. This name is consistent with the name of the test fixture module that is written later in the design flow by NGD2VER during post-NGDBuild, post-MAP, or post-route simulation. If this naming consistency is maintained, you can use the same test fixture file for simulation at all stages of the design flow with minimal modification
If you do not have a STARTUP block in your design, you should add the following to the test fixture module.
For post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation, you must omit the assign statement for the global reset signal. This is because the net connections exist in the post-NGDBuild design, and retaining the assign definition causes a possible conflict with these connections.
Note: The terms “test bench” and “test fixture” are used synonymously throughout this manual.
The following design shows how to drive the GSR signal in a testfixture file at the beginning of a pre-NGDBuild Unified Library functional simulation.
You should reference the global set/reset net as GSR in XC4000E/L/X, Spartan/XL, or Virtex designs without a STARTUP/STARTUP_VIRTEX block. The Verilog module defining the global net must be referenced as glbl.GSR because this is how it is modeled in the Verilog UniSims library.
In the design code, declare GSR as a Verilog wire, however, it is not specified in the port list for the module. Describe GSR to reset or set every inferred register or latch in your design. GSR does not need to be connected to any instantiated registers or latches, as shown in the following example.
module my_counter (CLK, D, Q, COUT);
input CLK, D;
output Q;
output [3:0] COUT;
wire GSR;
reg [3:0] COUT;
always @(posedge GSR or posedge CLK)
begin
if (GSR == 1'b1)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// FDCE instantiation
// GSR is modeled as a wire within a global module. So,
// CLR does not need to be connected to GSR and the flop
// will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
endmodule
Since GSR is declared as a floating wire and is not in the port list, the synthesis tool optimizes the GSR signal out of the design. GSR is replaced later by the implementation software for all post-implementation simulation netlists.
In the test fixture file, set GSR to test.uut.GSR (the name of the global set/reset signal, qualified by the name of the design instantiation instance name and the test fixture instance name). Since there is no STARTUP block, a connection to GSR is made in the testfixture via an assign statement.
`timescale 1 ns / 1 ps
module test;
reg CLK, D;
wire Q;
wire [3:0] COUT;
reg GSR;
assign glbl.GSR = GSR;
assign test.uut.GSR = GSR;
my_counter uut (.CLK (CLK), .D (D), .Q (Q), .COUT (COUT));
initial begin
$timeformat(-9,1,”ns”,12);
$display(“\t T C G D Q C”);
$display(“\t i L S O”);
$display(“\t m K R U”);
$display(“\t e T”);
$monitor(“%t %b %b %b %b %h”, $time, CLK, GSR, D, Q, COUT);
end
initial begin
CLK = 0;
forever #25 CLK = ~CLK;
end
initial begin
#0 {GSR, D} = 2'b11; #100 {GSR, D} = 2'b10; #100 {GSR, D} = 2'b00; #100 {GSR, D} = 2'b01;#100 $finish;
end
endmodule
In this example, the active high GSR signal in the XC4000 family device is activated by driving it high. 100 ns later, it is deactivated by driving it low. (100 ns is an arbitrarily chosen value.)
You can use the same test fixture for simulating at other stages in the design flow if this methodology is used.
For pre-NGDBuild functional simulation, the active High GR net in XC5200 devices should be simulated in the same manner as GSR for XC4000E/L/X, Spartan/XL, or Virtex.
In the design code, declare GR as a Verilog wire, however, it is not specified in the port list for the module. Describe GR to reset or set every inferred register or latch in your design. GR does not need to be connected to any instantiated registers or latches, as shown in the following example.
module my_counter (CLK, D, Q, COUT);
input CLK, D;
output Q;
output [3:0] COUT;
wire GR;
reg [3:0] COUT;
always @(posedge GR or posedge CLK)
begin
if (GR == 1'b1)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// FDCE instantiation
// GR is modeled as a wire within a global module. So,
// CLR does not need to be connected to GR and the flop
// will still be reset with GR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
endmodule
Since GR is declared as a floating wire and is not in the port list, the synthesis tool optimizes the GR signal out of the design. GR is replaced later by the implementation software for all post-implementation simulation netlists.
In the test fixture file, set GR to test.uut.GR (the name of the global set/reset signal, qualified by the name of the design instantiation instance name and the test fixture instance name). Since there is no STARTUP block, a connection to GR is made in the testfixture via an assign statement.
`timescale 1 ns / 1 ps
module test;
reg GR;
assign glbl.GR = GR;
assign test.uut.GR = GR;
.
.
.
initial begin
GR = 1; // if you wish to reset/set the device;
#100 GR = 0; // deactivate GR
end
In this example, the active high GR signal in the XC5200 family device is activated by driving it high. 100 ns later, it is deactivated by driving it low. (100 ns is an arbitrarily chosen value.).
You can use the same test fixture for simulating at other stages in the design flow if this methodology is used.
For pre-NGDBuild functional simulation, asserting global reset in XC3000A/L or XC3100A/L designs is almost identical to the procedure for asserting global reset in XC5200 designs, except that GR is active Low.
Note: The STARTUP block is not supported on XC3000A/L or XC3100A/L devices.
In the design code, declare GR as a Verilog wire, however, it is not specified in the port list for the module. Describe GR to reset or set every inferred register or latch in your design. GR does not need to be connected to any instantiated registers or latches, as shown in the following example.
module my_counter (CLK, D, Q, COUT);
input CLK, D;
output Q;
output [3:0] COUT;
wire GR;
reg [3:0] COUT;
always @(negedge GR or posedge CLK)
begin
if (GR == 1'b0)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// FDCE instantiation
// GR is modeled as a wire within a global module. So,
// CLR does not need to be connected to GR and the flop
// will still be reset with GR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
endmodule
Since GR is declared as a floating wire and is not in the port list, the synthesis tool optimizes the GR signal out of the design. Although this is correct in the hardware, it is actually an implicit connection, and not listed in the netlist (XNF or EDIF). GR is replaced later by the implementation software for all post-implementation simulation netlists.
In the test fixture file, set GR to test.uut.GR (the name of the global set/reset signal, qualified by the name of the design instantiation instance name and the test fixture instance name). Since there is no STARTUP block, a connection to GR is made in the testfixture via an assign statement.
`timescale 1 ns / 1 ps
module test;
reg GR;
assign glbl.GR = GR;
assign test.uut.GR = GR;
.
.
.
initial begin
GR = 0; // if you wish to reset/set the device;
#100 GR = 1; // deactivate GR
end
In this example, the active Low GR signal in the XC3000A/L and XC3100A/L family device is activated by driving it high. 100 ns later, it is deactivated by driving it low. (100 ns is an arbitrarily chosen value.).
The Global Reset (GR) signal in the XC3000A/L and XC3100A/L architecture is modeled differently in functional simulation netlists and SimPrims library-based netlists generated by NGD2VER. In the Verilog Unified Library, GR is modeled as a wire within a global module, while in a SimPrims-based netlist, it is always modeled as an external port. As a result, you cannot use the same test bench file for both Unified library simulation and SimPrims-based simulation.
If you do have a STARTUP block in your design, the signal you toggle is the external input port that controls the global reset pin of the STARTUP block. You should add the following to the test fixture module for RTL modeling of the global reset pin.
Note: The terms “test bench” and “test fixture” are used synonymously throughout this manual.
For post-NGDBuild functional simulation, post-map timing simulation, and post-route timing simulation, you must omit the assign statement for the global reset signal. This is because the net connections exist in the post-NGDBuild design, and retaining the assign definition causes a possible conflict with these connections.
By default for XC4000E/L/X, XC5200, Spartan/XL, and Virtex devices, the GSR/GR pin is active High. To change the polarity of these signals in your Verilog code, instantiate or infer an inverter to the net that sources the GSR/GR pin of the STARTUP block.
Figure 5.7 Inverted GSRThe inversion is absorbed inside the STARTUP block; a function generator is not used to generate the inverter.
In the following Verilog code, GSR is listed as a top-level port.
module my_counter (MYGSR, CLK, D, Q, COUT);
input MYGSR, CLK, D;
output Q;
output [3:0] COUT;
reg [3:0] COUT;
wire INV_GSR;
assign INV_GSR = !MYGSR; // Inverted GSR
// Modeling inverted GSR with RTL code
always @(posedge INV_GSR or posedge CLK)
begin
if (INV_GSR == 1'b1)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// FDCE instantiation
// GSR is modeled as a wire within a global module. So,
// CLR does not need to be connected to GSR and the flop
// will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
STARTUP U1 (.GSR (INV_GSR), .GTS (1'b0), .CLK (1'b0));
endmodule
In the following figure, MYGSR is an external user signal that controls GSR.
Figure 5.8 Verilog User-Controlled GSRIn the following Verilog code, GSR is listed as a top-level port. Synthesis sees a connection of GSR to the STARTUP and as well to the behaviorally described counter. Although this is correct in the hardware, it is actually an implicit connection, and GSR is only listed as a connection to the STARTUP in the netlist (XNF and EDIF).
module my_counter (MYGSR, CLK, D, Q, COUT);
input MYGSR, CLK, D;
output Q;
output [3:0] COUT;
reg [3:0] COUT;
always @(posedge MYGSR or posedge CLK)
begin
if (MYGSR == 1'b1)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// FDCE instantiation
// GSR is modeled as a wire within a global module. So,
// CLR does not need to be connected to GSR and the flop
// will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
STARTUP U1 (.GSR (MYGSR), .GTS (1'b0), .CLK (1'b0));
endmodule
The following is an example of controlling the global set/reset signal by driving the external MYGSR input port in a test fixture file at the beginning of an RTL or post-synthesis functional simulation when there is a STARTUP block in XC4000E/L/X and Spartan/XL designs, or the STARTUP_VIRTEX in Virtex.
The global set/reset control signal should be toggled High, then Low in an initial block.
`timescale 1 ns / 1 ps
module test;
reg GSR;
.
.
.
initial begin
GSR = 1; // if you wish to reset/set the device;
#100 GSR = 0; // deactivate GSR
end
In addition, a Verilog global signal called glbl.GSR is defined within the STARTUP/STARTUP_VIRTEX block to make the connection between the user logic and the global GSR net embedded in the Unified models. For post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation, glbl.GSR is defined in the Verilog netlist that is created by NGD2VER.
For XC5200 designs with a STARTUP block, you should simulate the net controlling GR in the same manner as for the XC4000E/L/X, Spartan/XL, and Virtex.
Substitute MYGR for MYGSR in Example 1 to obtain the testfixture fragment for simulating GR in a Verilog RTL or post-synthesis simulation.
Figure 5.9 Verilog User-Controlled Inverted GRIn addition, a Verilog global signal called glbl.GR is defined within the STARTUP block to make the connection between the user logic and the global GR net embedded in the Unified models. For post-NGDBuild functional simulation, post-map timing simulation, and post-route timing simulation, glbl.GR is defined in the Verilog netlist that is created by NGD2VER.
STARTUP is not supported or required in XC3000A/L and XC3100A/L designs. Follow the procedure for XC3000A/L and XC3100A/L designs without STARTUP blocks.