Setting Verilog Global Tristate (XC4000, Spartan, and XC5200 Outputs Only)

XC4000E/L/X, Spartan/XL, Virtex, and XC5200 devices also have a global control signal (GTS) that tristates all output pins. This allows you to isolate the actual device part during board level testing. You can also tristate the FPGA device outputs during board level simulation to assist in debugging simulation. In most cases, GTS is deactivated so that the outputs are active.

Although the STARTUP/STARTUP_VIRTEX component also gives you the option of controlling the global tristate net from an external pin, it is usually used for controlling global reset. In this case, you can leave the GTS pin unconnected in the design entry phase, and it will float to its inactive state level. The global tristate net, GTS, is implemented in designs even if a STARTUP/STARTUP_VIRTEX block is not instantiated. You can deactivate GTS by driving it low in your test fixture file, or by connecting the GTS pin to GND in your input design

Defining GTS in a Test Bench

For pre-NGDBuild UniSim functional simulation, you must set the value of the appropriate Verilog global signal, glbl.GTS, to the name of the GTS net, qualified by the appropriate scope identifiers.

The scope identifiers are a combination of the test module scope and the design instance scope. The scope qualifiers are required because the scope information is needed when the glbl.GTS wire is interpreted by the Verilog UniSim simulation models to emulate a global tri-state signal.

For post-NGDBuild and post-route timing simulation, the testfixutre template (.tv file) produced by running NGD2VER with the -tf option contains most of the code previously described for defining and toggling GTS.

The general procedure for specifying GTS is similar to that used for specifying the global set/reset signals, GSR and GR. You define the global tristate signal with Verilog global module, glbl.GTS. If you do not want to specify GTS for simulation, you do not need to change anything in your design or testfixture.

The GTS signal in XC4000E/L/X, Spartan/XL, Virtex, and XC5200 devices is active High. This global module is not used in timing simulation when there is a STARTUP/STARTUP_VIRTEX block in your design and the GTS pin is connected.

Designs without a STARTUP Block

If you do not have a STARTUP block in your design, you should add the following to the test fixture module.

reg GTS;

assign glbl.GTS = GTS;

assign testfixture_name.instance_name.GTS = GTS;

// Only for RTL simulation modeling of GTS

For post-NGDBuild functional simulation, post-map timing simulation, and post-route timing simulation, you must omit the assign statement for the global tri-state signal. This is because the net connections exist in the post-NGDBuild design, and retaining the assign definition causes a possible conflict with these connections.

Note: The terms “test bench” and “test fixture” are used synonymously throughout this manual.

XC4000E/L/X, Spartan/XL, Virtex and XC5200 RTL Functional Simulation (No STARTUP Block)

You can drive the GTS signal in a test fixture file at the beginning of a pre-NGDBuild RTL or post-synthesis functional simulation. The global tristate net is named GTS in XC4000E/L/X, Spartan/XL, Virtex, and XC5200 designs. The Verilog module defining the global tri-state net must be referenced as glbl.GTS because this is how it is modeled in the Verilog UniSim library.

Designs with a STARTUP Block

If you do have a STARTUP block in your design, the signal you toggle at the beginning of simulation is the port or signal in your design that is used to control global tristate. This is usually an external input port in the Verilog netlist, but can be a wire if global tristate is controlled by internal logic in your design. A Verilog global signal called glbl.GTS is defined within the STARTUP block to make the connection between the user logic and the global GTS net embedded in the Unified models

Example 1: XC4000E/L/X, Spartan/XL, Virtex, and XC5200 Simulation (With STARTUP/STARTUP_VIRTEX, GTS Pin Connected)

In the following figure, MYGTS is an external user signal that controls GTS.

Figure 5.10 Verilog User-Controlled Inverted GTS

The following is an example of controlling the global tri-state signal by driving the external MYGTS input port in a test fixture file at the beginning of an RTL or post-synthesis functional simulation when there is a STARTUP block in XC4000E/L/X and Spartan/XL design, or the STARTUP_VIRTEX in Virtex. The global GTS model in the UniSim simulation models for output buffers (OBUF, OBUFT, and so on).

The global tri-state control signal should be toggled High, then Low in an initial block.

module test;

reg MYGTS;

.

.

.

initial begin

MYGTS = 1; // if you wish to tristate the device;

#100 MYGTS = 0;     // deactivate GTS

end

Example 2: XC4000E/L/X, Spartan/XL, Virtex, and XC5200 Simulation (With STARTUP/STARTUP_VIRTEX, GTS Pin not connected)

A Verilog global signal called glbl.GTS is defined within the STARTUP/STARTUP_VIRTEX block to make the connection between the user logic and the global GTS net embedded in the Unified models. For post-NGDBuild functional simulation, post-map timing simulation, and post-route timing simulation, glbl.GTS is defined in the Verilog netlist that is created by NGD2VER.

module test;

reg GTS;

assign glbl.GTS = GTS;

.

.

.

initial begin

GTS = 1; // if you wish to tristate the device;

#100 GTS = 0;     // deactivate GTS

end

Note: For post-route timing simulation, you can use the same test bench.