For some Verilog simulators, such as NC-Verilog and ModelSim, you may need to compile the Verilog libraries before you can use them for design simulations. A pre-compiled library methodology has the advantage of speeding up the simulation of your designs. You do not need to compile the libraries for Verilog-XL because it uses an interpretive compilation of the libraries. To simulate Xilinx designs, you need the following simulation libraries.
For detailed instructions on compiling these simulation libraries, see the instructions in Xilinx Solution # 1923 which is available at http://www.xilinx.com/techdocs/1923.htm.
After compiling the libraries, notice that ModelSim creates a file called modelsim.ini. View this file and notice that the upper portion defines the locations of the compiled libraries. When doing a simulation, you must provide the modelsim.ini file either by copying the file directly to the directory where the HDL files are to be compiled and the simulation is to be run, or by setting the MODELSIM environment variable to the location of your master .ini file. You must set this variable since the ModelSim installation does not initially declare the path for you. For UNIX, type the following.
setenv MODELSIM /path/to/the/modelsim.ini