Functional Simulation

Functional simulation of HDL designs includes support for FPGA and CPLD architecture features, such as global set/reset, global tristate enable, on-chip oscillators, RAMs, and ROMs.

You can perform functional simulation at the following points in the design flow.

• RTL simulation, including instantiated UniSim library components, LogiBLOX modules, and LogiCORE models
  
  
• Post-synthesis gate-level VHDL or Verilog netlist
  
  
• Post-NGDBuild gate-level VHDL or Verilog netlist from implementation after NGDBuild using the SimPrim library
  
  
• Post-map partial-timing functional simulation with netlist and SDF file from implementation after mapping, and before place and route, using the SimPrim library
  
  

Register Transfer Level (RTL)

The first simulation point is the RTL-level simulation that allows you to verify or simulate a description at the system or chip level. At this level, the system or chip is described with high-level RTL language constructs. VHDL and Verilog simulators exercise the design to check its functionality before it is implemented in gates. A test bench is created to model the environment of the system or chip. At this level, the Unified Simulation Library (UniSim) is used to instantiate cells. You can also instantiate LogiBLOX components if you do not want to rely on the module generation capabilities of your synthesis tool, or if your design requires larger memory structures.

Post-Synthesis (Pre-NGDBuild) Gate-Level Simulation

After the RTL simulation is error-free, the system or chip is synthesized to gates. The test bench is used again to simulate the synthesized result and check its consistency with the original design description.

Gate-level simulation in the Xilinx design flow includes any simulation performed after any of the synthesis, map, or place and route stages. The post-synthesis pre-NGDBuild gate-level simulation is a functional simulation with unit delay timing. The gates are expressed in terms of UniSim components.

This gate-level functional simulation allows you to directly verify your design after it has been generated by the synthesis tool. If there are differences in the behavior of the original RTL description and the synthesized design, this may indicate a problem with the synthesis tool. Although RTL-level and gate-level simulation may differ even when the synthesis is correct. This is due to the change in the level of abstraction. In general, overall functionality should be the same, but timing differences may occur.

Post-synthesis simulation is synthesis vendor-dependent, and the synthesis tool must write VHDL or Verilog netlists in terms of UniSim library components. Check with your synthesis vendor for this feature. The library usage guidelines for RTL simulation also apply to post-synthesis pre-NGDBuild gate-level functional simulation. LogiBLOX models remain as behavioral blocks and can be simulated in the same design as structural UniSim components. You may have to insert library statements into the HDL code.

Post-NGDBuild (Pre-Map) Gate-Level Simulation

The post-NGDBuild (pre-map) gate-level functional simulation is used when it is not possible to simulate the direct output of the synthesis tool. This occurs when the tool cannot write UniSim-compatible VHDL or Verilog netlists. In this case, NGDBuild translates the EDIF or XNF output of synthesis to SimPrim library components. Like post-synthesis, pre-NGDBuild simulation, this simulation allows you to verify that your design has been synthesized correctly, and you can begin to identify any differences due to the lower level of abstraction. Unlike the post-synthesis pre-NGDBuild simulation, there are GSR, GR (global reset), PRLD (preload), and GTS nets that must be initialized, just as for post-map partial timing simulation.

Different simulation libraries are used to support simulation before and after running NGDBuild. Prior to NGDBuild, your design is expressed as a UniSim netlist containing Unified Library components. After NGDBuild, your design is a netlist containing SimPrims. Although these library changes are fairly transparent, two important considerations are specifying different simulation libraries for pre- and post-implementation simulation, and the different gate-level cells in pre- and post-implementation netlists.

You can pause the implementation tools after reading in your source files; select either a VHDL or Verilog netlist as an output file; and write the file.

Post-Map Partial Timing (CLB and IOB Block Delays)

The third type of post-synthesis functional simulation is post-map partial timing simulation. This gate-level description is also expressed in terms of SimPrim components.

The SDF file that is created contains timing numbers for the CLB and IOB mapped blocks. At this point, your design is not routed and does not contain net delays, except for pre-laid out macros, such as cores. Like the post-NGDBuild and full-timing simulation, there are GSR, GR, PRLD, and GTS nets that must be initialized. If you want partial timing delays, you can use the SDF file (this is optional).

You can pause the implementation tools after the Map program stops, and write one of the HDL formats.

Creating a Simulation Test Bench

When you create a test bench for functional simulation, refer to the following table for coding style examples. You should refer to your synthesis vendor's documentation before using these styles because many of the styles cannot be synthesized.

Table 5_2 Common Coding Examples for Verilog/VHDL