Timing Simulation

Timing simulation is important in verifying the operation of your circuit after the worst-case placed and routed delays are calculated for your design. In many cases, you can use the same test bench that you used for functional simulation to perform a more accurate simulation with less effort. You can compare the results from the two simulations to verify that your design is performing as initially specified. The Xilinx tools create a VHDL or Verilog simulation netlist of your placed and routed design, and provide libraries that work with many common HDL simulators.

Post-Route Full Timing (Block and Net Delays)

After your design is routed using PAR, it can be simulated with the actual block and net timing delays with the same test bench used in the behavioral simulation.

The back-annotation process (NGDAnno) produces a netlist of SimPrims annotated with an SDF file with the appropriate block and net delay data from the place and route process. This netlist has GSR, GR, PRLD, and GTS nets that must be initialized. For more information, refer to the “Simulating Global Signals” section.

Creating a Timing Simulation Netlist

You can create a timing simulation netlist from the Design Manager or from the command line, as described in this section.

From the Design Manager

1. Select Setup Options in the Flow Engine.
   
   The Options dialog box appears.
   
   
2. Select the Produce Timing Simulation Data button in the Optional Targets field.
   
   
3. Select the Edit Template button next to the Implementation drop-down list in the Program Options Templates field.
   
   The Implementation Template dialog box appears.
   
   
4. Select the Interface tab.
   
   
5. In the Simulation Data Options field, select applicable options as follows.
   
   
   • Format
     
     Specify the netlist format to use for simulation. The format is usually VHDL or Verilog for synthesis designs.
     
     
   • Correlate Simulation Data to Input Design
     
     This option enables signal back annotation to the original compiled netlist. By default, this option is on. However, you can turn if off to decrease run time, or if there are problems with the back-annotated simulation data. Port names are not changed by this option; however, internal node names may change.
     
     
   • Bring Out Global Set/Reset Net as a Port
     
     This option creates an external port in the simulation netlist to allow control of the power-on reset from a port. This option is not necessary for most simulators, and is off by default.
     
     
6. Click OK in the Implementation Template dialog box.
   
   
7. Click OK in the Options dialog box.
   
   
8. When you implement your design, the Flow Engine produces timing simulation data files.
   
   

   Note: If you are using the Verilog-XL simulator, you may want to use the -ul switch for the NGD2VER program to automatically add the uselib directive to the simulation netlist to point to the location of the simulation libraries. Use the Template Manager to set this switch. Refer to the Design Manager/Flow Engine Guide or http://www.xilinx.com/techdocs/3167.htm for more information.

From the Command Line

Note: To display the available options for the programs in this section, enter the program executable name at the prompt without any arguments. For complete descriptions of these options, refer to the Development System Reference Guide.

1. Run NGDAnno on your placed and routed .ncd file.
   
   For back-annotated output (signals correlated to original netlist), enter the following.
   
   ngdanno -p design.pcf design.ncd design.ngm
   
   For output that is not back-annotated (faster run time), enter the following.
   
   ngdanno design.ncd
   
   
2. Run the NGD2XXX program for the particular netlist you want to create.
   
   For VHDL, enter the following.
   
   ngd2vhdl [options] design.nga
   
   For Verilog, enter the following.
   
   ngd2ver [options] design.nga