Introduction

Xilinx supports functional and timing simulation of HDL designs at the following three points in the HDL design flow as shown in the following figure.

• Register Transfer Level (RTL) simulation which may include the following.
  
  
  • Instantiated UniSim library components
    
    
  • LogiBLOX modules
    
    
  • LogiCORE models
    
    
• Post-synthesis functional simulation with one of the following.
  
  
  • Gate-level UniSim library components
    
    or
    
    
  • Gate-level pre-route SimPrim library components
    
    
• Post-implementation back-annotated timing simulation with the following.
  
  
  • SimPrim library components
    
    
  • Standard Delay Format (SDF) file
    
    

    Figure 5.1 Three Simulation Points for HDL Designs

The three primary simulation points can be expanded to allow for two additional post-synthesis simulations, as shown in the following table. These two additional points can be used when the synthesis tool either cannot write VHDL or Verilog, or if the netlist is not in terms of UniSim components.

Table 5_1 Five Simulation Points in HDL Design Flow

These simulation points are described in detail in the “Functional Simulation” section and the “Timing Simulation” section. The libraries required to support the simulation flows are described in detail in the “Using VHDL/Verilog Libraries and Models” section. The new flows and libraries now support closer functional equivalence of initialization behavior between functional and timing simulations. This is due to the addition of new methodologies and library cells to simulate GSR/GTS behavior.

It is important to address the built-in reset circuitry behavior in your designs starting with the first simulation to ensure that the simulations agree at the three primary points.

If you do not simulate GSR behavior prior to synthesis and place and route, your RTL and possibly post-synthesis simulations will not initialize to the same state as your post-route timing simulation. As a result, your various design descriptions are not functionally equivalent and your simulation results will not match. In addition to the behavioral representation for GSR, you need to add a Xilinx implementation directive. This directive is used to specify to the place and route tools to use the special purpose GSR net that is pre-routed on the chip, and not to use the local asynchronous set/reset pins. Some synthesis tools can identify, from the behavioral description, the GSR net, and will place the STARTUP module on the net to direct the implementation tools to use the global network. However, other synthesis tools interpret behavioral descriptions literally, and will introduce additional logic into your design to implement a function. Without specific instructions to use device global networks, the Xilinx implementation tools will use general purpose logic and interconnect resources to redundantly build functions already provided by the silicon.

Even if GSR behavior is not described, the actual chip initializes during configuration, and the post-route netlist will have this net that must be driven during simulation. The “Simulating Global Signals” section includes the methodology to describe this behavior, as well as the GTS behavior for output buffers.

Xilinx VHDL simulation supports the VITAL standard. This standard allows you to simulate with any VITAL-compliant simulator, including MTI/Mentor^® ModelSim, Synopsys VSS, and Active-VHDL.

Built-in Verilog support allows you to simulate with the Cadence Verilog-XL and other compatible simulators. Xilinx HDL simulation supports all current Xilinx FPGA and CPLD devices. Refer to the “Using VHDL/Verilog Libraries and Models” section for the list of supported VHDL and Verilog standards.