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The five simulation points listed previously require the UniSim, SimPrim, XDW (Xilinx DesignWare), and LogiBLOX libraries. The first point, RTL simulation, is a behavioral description of your design at the register transfer level. RTL simulation is not architecture-specific unless your design contains instantiated UniSim or LogiBLOX components. To support these instantiations, Xilinx provides a functional UniSim library and a behavioral LogiBLOX library.
The second point, post-synthesis (pre-NGDBuild) gate-level simulation uses the UniSim and XDW libraries. The third, fourth, and fifth points (post-NGDBuild, post-map, and post-route) use the SimPrim library. The following table indicates what library is required for each of the five simulation points.
| Simulation Point | Compilation Order of Library Required |
|---|---|
| RTL | UniSim LogiBLOX |
| Post-Synthesis | UniSim (Device dependent) |
| Post-NGDBuild | SimPrim |
| Post-MAP | SimPrim |
| Post-Route | SimPrim |
The standards in the following table are supported by the Xilinx simulation flow.
| Description | Version |
|---|---|
| VHDL Language | IEEE-STD-1076-87 |
| Verilog Language | IEEE-STD-1364-95 |
| VITAL Modeling Standard | IEEE-STD-1076.4-95 |
| Standard Delay Format (SDF) | 2.1 |
| Std_logic Data Type | IEEE-STD-1164-93 |
The UniSim and SimPrim libraries adhere to IEEE-STDs. The VHDL library uses the VITAL IEEE-STD-1076.4 standard, and the Verilog library uses the IEEE-STD-1364 standard. By following these standards, Xilinx provides support for customers who use HDL tools from various vendors.
VHDL Initiative Towards ASIC Libraries (VITAL) was created to promote the standardization and interchangeability of VHDL libraries and simulators from various vendors. It also defines a standard for timing back-annotation to VHDL simulators.
Most simulator vendors have agreed to use the IEEE-STD 1076.4 VITAL standard for the acceleration of gate-level simulations. Check with your simulator vendor to confirm that this standard is being followed, and to verify proper settings and VHDL packages for this standard. The simulator may also accelerate IEEE-STD-1164, the standard logic package for types.
VITAL libraries include some overhead for timing checks and back-annotation styles. The UniSim Library turns these timing checks off for unit delay functional simulation. The SimPrim back-annotation library keeps these checks on by default; however, you or your system administrator can turn them off. You must edit and re-compile the SimPrim components file after setting the generics.
The following table provides information on the location of the simulation library source files, as well as the order for a typical compilation.
| Library | Location of Source Files | Required Libraries | ||
|---|---|---|---|---|
| Verilog | VITAL VHDL | Verilog | VITAL VHDL | |
| UniSim 4K Family, Spartan (use UNI4000E for Spartan) | $XILINX/ verilog/src/unisims | $XILINX/ vhdl/src/ unisims | Not required for Verilog-XL; see vendor documentation for other simulators | Required; typical compilation order: unisim_VCOMP.vhd unisim_VPKG.vhd unisim_VITAL.vhd unisim_VCFG4K.vhd (optional) |
| UniSim 52K Family | $XILINX/ verilog/src/ uni5200 | $XILINX/ vhdl/src/ unisims | Not required for Verilog-XL; see vendor documentation for other simulators | Required; typical compilation order: unisim_VCOMP52K.vhd unisim_VITAL.vhd unisim_VITAL52K.vhd unisim_VCFG52K.vhd |
| LogiBLOX (Device Independent) | None; uses SimPrim library | $XILINX/ vhdl/src/ logiblox | None; uses SimPrim library | Required; typical compilation order: mvlutil.vhd mvlarith.vhd logiblox.vhd |
| SimPrim (Device Independent) | $XILINX/ verilog/src/ simprims | $XILINX/ vhdl/src/ simprims | Not required for Verilog-XL; see vendor documentation for other simulators | Required; typical compilation order: simprim_Vcomponents.vhd simprim_Vpackage.vhd simprim_VITAL.vhd |
The UniSim Library, used for functional simulation only, contains default unit delays. This library includes all the Xilinx Unified Library components that are inferred by most popular synthesis tools. In addition, the UniSim Library includes components that are commonly instantiated, such as IOs and memory cells. You should use your synthesis tool's module generators (such as LogiBLOX) to generate higher order functions, such as adders, counters, and large RAMs.
The UniSim library directory structure is different for VHDL and Verilog. There is only one VHDL library for all Xilinx technologies because the implementation differences between architectures are not important for unit delay functional simulation except in a few cases where functional differences occur.
For example, the decode8 in XC4000 devices has a pull-up, and in XC5200 devices, it does not. In these few cases, configuration statements are used to choose between architectures for the components. One library makes it easy to switch between technologies. It is left up to the user and the synthesis tool to use technology-appropriate cells. For Verilog, separate libraries are provided for each technology because Verilog does not have a configuration statement.
Schematic macros are not provided because most schematic vendors provide the lower-level netlist for importing into a synthesis tool. Some synthesis vendors have these macros in their libraries, and can expand them to gates. You can use the HDL output from synthesis to simulate these macros. You can also use a post-NGDBuild or post-Map netlist to simulate netlists with embedded schematic macros. This lower-level netlist for a schematic macro is also required for implementation. The VHDL models for Synopsys DesignWare components are in the Xilinx Synopsys Interface at $XILINX/synopsys/libraries/sim/src/xdw. Because Verilog versions of the DesignWare components are not currently available, use post-NGDBuild functional simulation instead.
Note: Verilog reserves the names buf, pullup, and pulldown; the Xilinx versions are changed to buff, pullup1, pullup2, or pulldown2, and then mapped to the proper cell during implementation.
The UniSim VHDL library (or Verilog library) can be compiled to any physical location. The VHDL source files are found in $XILINX/vhdl/src/unisims and are listed here in the order in which they must be compiled.
Note: To use both 4K and 52K, compile them into separate directories as a UniSim library. Change the mapping of the UniSim logical name to the appropriate directory for each design.
The uppercase Verilog components are found in individual component files in the following directories.
You can instantiate UniSim library components in your design and simulate them during RTL simulation. Your VHDL code must refer to the UniSim library compiled by you or by your system administrator. The VHDL simulation tool must map the logical library to the physical location of the compiled library. VHDL component declarations are provided in the library and do not need to be repeated in your code. Verilog must also map to the UniSim Verilog library.
LogiBLOX is a module generator used for schematic-based design entry of modules such as adders, counters, and large memory blocks. In the HDL flow, you can use LogiBLOX to generate large blocks of memory for instantiation. Refer to the LogiBLOX Guide for more information.
In addition to the RTL code that results in synthesized logic, you can generate modules such as counters, adders, and large memory arrays with LogiBLOX. You can enter the desired parameters into LogiBLOX and select a VHDL model as output. The VHDL model is at the behavioral level because it allows for quicker simulation times. LogiBLOX is primarily useful for building large memory arrays that cannot be inferred. VHDL models are provided for LogiBLOX modules from the schematic environment, or for large memory arrays. Most LogiBLOX modules contain registers and require the global set/reset (GSR) initialization. Since the modules do not contain output buffers going off-chip, the global tristate enable (GTS) initialization does not apply.
LogiBLOX models begin as behavioral in VHDL, but are mapped to SimPrim structural models in the back-annotated netlist. The behavioral model is also used for any post-synthesis simulation because the module is processed as a “black box” during synthesis. It is important that the initialization behavior is consistent for the behavioral model used for RTL and post-synthesis simulation and for the structural model used after implementation. In addition, the initialization behavior must work with the method used for synthesized logic and cores.
Note: For Verilog, the LogiBLOX model is a structural netlist of SimPrim models. Do not synthesize this netlist; it is for functional simulation only.
The LogiBLOX library is not a library of modules. It is a set of packages required by the LogiBLOX models that are created “on-the-fly” by the LogiBLOX tool.
You can compile the LogiBLOX VHDL library (or Verilog) to any specified physical location. The VHDL source files are in $XILINX/vhdl/src/logiblox, and are listed below in the order in which they must be compiled.
The Verilog source files are in $XILINX/verilog/src/logiblox.
LogiBLOX components are simulated with behavioral code. They are not intended to be synthesized, but they can be simulated. The synthesizer processes the components as a “black box”. Implementation uses the NGO file created by LogiBLOX. The source libraries for LogiBLOX packages are in $XILINX/vhdl/src/logiblox and $XILINX/verilog/src/logiblox. The actual models are output from the LogiBLOX tool. The package files must be compiled into a library named logiblox. The component model from the LogiBLOX GUI should be compiled into your working directory with your design.
In addition to synthesized or generated logic, you can use high-level pre-designed LogiCORE models. These models are high-level VHDL behavioral or RTL models that are mapped to SimPrim structural models in the back-annotated netlist. The behavioral model is used for any post-synthesis simulation because synthesis processes the core as a “black box”. As with LogiBLOX models, the initialization behavior must be consistent for the behavioral model used for RTL and post-synthesis simulation and for the structural model used after implementation. In addition, the initialization behavior must work with the method used for synthesized logic and LogiBLOX modules.
The UniSim VHDL and Verilog libraries can emulate the global set/reset and global tristate network in Xilinx FPGAs. VHDL uses special components for driving the local reset and tristate enable lines, and sending implementation directives to move the nets to the global signal resources. Verilog uses a macro definition.
The local signals emulate the fully routed global signals in a post-routed netlist. Both the VHDL and Verilog post-route netlists use the SimPrim Library and have global reset and output tristate enable signals fully routed; they are not emulated.
LogiBLOX and LogiCORE models are at a behavioral level and do not use library components for global signals. However the LogiBLOX model does require the packages that are compiled into the LogiBLOX library.