Simulating Global Signals

Xilinx PLDs have register (flip-flops and latches) set/reset circuitry that pulses at the end of the configuration mode and after power-up. This pulse is automatic and does not need to be programmed. All the flip-flops and latches in a PLD receive this pulse through a dedicated global set/reset (GSR), PRLD, or reset (GR) net. The registers either set or reset, depending on how the registers are defined.

In addition to the set/reset pulse, all output buffers are tristated during configuration mode and after power-up with the dedicated global output tristate enable (GTS) net. The global tri-state and reset net names are provided in the following table.

Table 5_6 Global Reset and Tristate Names for Xilinx Devices

These PRLD, GSR, and GR nets require special handling during synthesis, simulation, and implementation to prevent them from being assigned to normally routed nets, which uses valuable routing resources and degrades design performance. The GSR, PRLD, or GR net receives a reset-on-configuration pulse from the initialization controller, as shown in the following figure.

Figure 5.2 Built-in FPGA Initialization Circuitry

This pulse occurs during the configuration or power-up mode of the PLD. However, for ease of simulation, it is usually inserted at time zero of the test bench, before logical simulation is initiated. The pulse width is device-dependent and can vary widely, depending on process voltage and temperature changes. The pulse is guaranteed to be long enough to overcome all net delays on the reset special-purpose net. The parameter for the pulse width is TPOR, as described in The Programmable Logic Data Book.

The tristate-on-configuration circuit shown in the “Built-in FPGA Initialization Circuitry” figure also occurs during the configuration or power-up mode of the PLD. Just as for the reset-on-configuration simulation, it is usually inserted at time zero of the test bench before logical simulation is initiated. The pulse drives all outputs to the tristate condition they are in during the configuration of the PLD. All general-purpose outputs are affected whether they are regular, tristate, or bi-direct outputs during normal operation. This ensures that the outputs do not erroneously drive other devices as the PLD is being configured. The pulse width is device-dependent and can vary widely with process and temperature changes. The pulse is guaranteed to be long enough to overcome all net delays on the GTS net. The generating circuitry is separate from the reset-on-configuration circuit. The pulse width parameter is T_POR, as described in The Programmable Logic Data Book. Simulation models use this pulse width parameter for determining HDL simulation for global reset and tri-state circuitry (initially developed for schematic design.)