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There are no global set/reset or output tristate enable pins on the simulation, synthesis, or implementation models of the register components in schematic-based designs. During synthesis, both the global and local reset and tristate-state enable signals are connected to the local pin. Schematic simulators can simulate global signals without a pin. The global signals are represented as internal signals in the schematic simulation model and the test vectors drive the internal global signals directly. If you want complete control of initialization, use registers with asynchronous set/reset to emulate the GSR, even if local set/reset is not required. Synchronous set/reset registers will initialize on their own at time zero. They can be synchronously set after that but cannot emulate GSR behavior after time zero. Some memory components without asynchronous clears will exhibit similar behavior.
In VHDL designs, you must declare as ports any signals that are stimulated or monitored from outside a module. Global GSR and GTS signals are used to initialize the simulation and require access ports if controlled from the test bench. However, the addition of these ports makes the pre- and post-implementation versions of your design different, and your original test bench is no longer applicable to both versions of your design. Since the port lists for the two versions of your design are different, the socket in the test bench matches only one of them. To address this issue, five new cells are provided for VHDL simulation: ROC, ROCBUF, TOC, TOCBUF, and STARTBUF.
Verilog can simulate internal signals, and these signals are driven directly from the test bench. However, interpretive Verilog (such as Verilog-XL) and compiled Verilog (such as MTI or NC-Verilog) require a different approach for handling the libraries.
You do not need to incorporate any ports into schematic designs for simulators to mimic the device's global reset (GSR) or global tristate (GTS) networks. Schematic simulators specify these signals on the register model as `global' to indicate to the simulator that these signals are all connected. These signals are not part of the cell's pin list, do not appear in the netlist, and are not implemented in the resulting design. These global signals are mapped into the equivalent signals in the back-end simulation model. Using this methodology with schematic designs, you can fully simulate the silicon's built-in global networks and implement your design without causing congestion of the general-purpose routing resources and degrading the clock speed.