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Oscillator output can vary within a fixed range. This cell is not included in the SimPrim library because you cannot drive global signals in VHDL designs. Schematic simulators can define and drive global nets so the cell is not required. Verilog has the ability to drive nets within a lower level module as well. Therefore the oscillator cells are only required in VHDL. After back-annotation, their entity and architectures are contained in your design's VHDL output. For functional simulation, they can be instantiated and simulated with the UniSim Library.
The period of the base frequency must be set in order for the simulation to proceed, since the default period of 0 ns disables the oscillator. The oscillator's frequency can vary significantly with process and temperature.
Before you set the base period parameter, consult The Programmable Logic Data Book for the part you are using. For example, the section in The Programmable Logic Data Book for the XC4000 Series On-Chip Oscillator states that the base frequency can vary from 4MHz to 10 MHz, and is nominally 8 MHz. This means that the base period generic “period_8m” in the XC4000E OSC4 VHDL model can range from 250ns to 100ns. An example of this follows.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
entity test1 is
port (DATAIN: in STD_LOGIC;
DATAOUT: out STD_LOGIC);
end test1;
architecture inside of test1 is
signal RST: STD_LOGIC;
component ROC
port(O: out STD_LOGIC);
end component;
component OSC4
port(F8M: out STD_LOGIC);
end component;
signal internalclock: STD_LOGIC;
begin
U0: ROC port map (RST);
U1: OSC4 port map (F8M=>internalclock);
process(internalclock)
begin
if (RST='1') then
DATAOUT <= '0';
elsif(internalclock'event and internalclock='1') then
DATAOUT <= DATAIN;
end if;
end process;
end inside;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
entity test_oftest1 is end test_oftest1;
architecture inside of test_oftest1 is
component test1
port(DATAIN: in STD_LOGIC;
DATAOUT: out STD_LOGIC);
end component;
signal userdata, userout: STD_LOGIC;
begin
UUT: test1 port map(DATAIN=>userdata,DATAOUT=>userout);
myinput: process
begin
userdata <= '1';
wait for 299 ns;
userdata <= '0';
wait for 501 ns;
end process;
end inside;
configuration overall of test_oftest1 is
for inside
for UUT:test1
for inside
for U0:ROC use entity UNISIM.ROC(ROC_V)
generic map (WIDTH=> 52 ns);
end for;
for U1:OSC4 use entity UNISIM.OSC4(OSC4_V)
generic map (PERIOD_8M=> 25 ns);
end for;
end for;
end for;
end for;
end overall;
This configuration is for pre-NGDBuild simulation. A similar configuration is used for post-NGDBuild simulation. The ROC, TOC, and OSC4 are mapped to the WORK library, and corresponding architecture names may be different. Review the .vhd file created by NGD2VHDL for the current entity and architecture names for post-NGDBuild simulation.