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For information on setting Global Set/Reset for FPGAs, see the “Setting Verilog Global Set/Reset” section of the Synthesis and Simulation Design Guide.
For information on setting Global Tristate for FPGAs, see the “Setting Verilog Global Tristate (XC4000, Spartan, and XC5200 Outputs Only)” section of the Synthesis and Simulation Design Guide.
For information on setting Global PRLD for CPLDs, refer to the “Simulating Your Design” chapter of the CPLD Synthesis Design Guide.