Chapter 1

Xilinx Unified Libraries

This chapter describes the Unified Libraries and the applicable device architectures for each library. It also briefly discusses the contents of the other chapters, the general naming conventions, and performance issues.

This chapter consists of the following major sections.

• “Overview”
  
  
• “Applicable Architectures”
  
  
• “Selection Guide”
  
  
• “Design Elements”
  
  
• “Schematic Examples”
  
  
• “Naming Conventions”
  
  
• “Attributes, Constraints, and Carry Logic”
  
  
• “Flip-Flop, Counter, and Register Performance”
  
  
• “Unconnected Pins”