Synthesis and Simulation Design Guide

About this Manual

This manual provides a general overview of designing Field Programmable Gate Arrays (FPGAs) with Hardware Description Languages (HDLs). It includes design hints for the novice HDL user, as well as for the experienced user who is designing FPGAs for the first time.

The design examples in this manual were created with Verilog and VHSIC Hardware Description Language (VHDL); compiled with various synthesis tools; and targeted for XC4000, Spartan, and XC5200 devices. Xilinx equally endorses both Verilog and VHDL. VHDL may be more difficult to learn than Verilog and usually requires more explanation.

This manual does not address certain topics that are important when creating HDL designs, such as the design environment; verification techniques; constraining in the synthesis tool; test considerations; and system verification. Refer to your synthesis tool's reference manuals and design methodology notes for additional information.

Before using this manual, you should be familiar with the operations that are common to all Xilinx software tools. These operations are covered in the Quick Start Guide.

Additional Resources

For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this page. You can also directly access some of these resources using the provided URLs.

Resource	Description/URL
Tutorial	Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm
Answers Database	Current listing of solution records for the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm
Application Notes	Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Book	Pages from The Programmable Logic Data Book, which describe device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/partinfo/databook.htm
Xcell Journals	Quarterly journals for Xilinx programmable logic users http://support.xilinx.com/xcell/xcell.htm
Tech Tips	Latest news, design tips, and patch information on the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm

Manual Contents

Chapter 1, “Getting Started,” provides a general overview of designing Field Programmable Gate Arrays (FPGAs) with HDLs. This chapter also includes installation requirements and instructions.
Chapter 2, “HDL Coding Hints,” includes HDL coding hints and design examples to help you develop an efficient coding style.
Chapter 3, “Understanding High-Density Design Flow,” provides synthesis and Xilinx implementation techniques to increase design performance and utilization.
Chapter 4, “Designing FPGAs with HDL,” includes coding techniques to help you improve synthesis results.
Chapter 5, “Simulating Your Design,” describes simulation methods for verifying the function and timing of your designs.
Appendix A, “Accelerate FPGA Macros with One-Hot Approach,” reprints an article describing one-hot encoding in detail.
Appendix B, “Report Files,” includes area and timing report files from various synthesis vendors.

Conventions

This manual uses the following typographical and online document conventions. An example illustrates each typographical convention.

Typographical

The following conventions are used for all documents.

Courier font indicates messages, prompts, and program files that the system displays.

speed grade: -100
Courier bold indicates literal commands that you enter in a syntactical statement. However, braces “{ }” in Courier bold are not literal and square brackets “[ ]” in Courier bold are literal only in the case of bus specifications, such as bus [7:0].

rpt_del_net=

Courier bold also indicates commands that you select from a menu.

File Open
Italic font denotes the following items.
- Variables in a syntax statement for which you must supply values
  
  edif2ngd design_name
- References to other manuals
  
  See the Development System Reference Guide for more information.
- Emphasis in text
  
  If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
Square brackets “[ ]” indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.

edif2ngd [option_name] design_name
Braces “{ }” enclose a list of items from which you must choose one or more.

lowpwr ={on|off}
A vertical bar “|” separates items in a list of choices.

lowpwr ={on|off}
A vertical ellipsis indicates repetitive material that has been omitted.

IOB #1: Name = QOUT' IOB #2: Name = CLKIN' . . .
A horizontal ellipsis “. . .” indicates that an item can be repeated one or more times.

allow block block_name loc1 loc2 ... locn;

Online Document

The following conventions are used for online documents.

Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.