Chapter 4

Designing FPGAs with HDL

This chapter includes coding techniques to help you improve synthesis results. It includes the following sections.

• “Introduction”
  
  
• “Using Global Low-skew Clock Buffers”
  
  
• “Using Dedicated Global Set/Reset Resource”
  
  
• “Encoding State Machines”
  
  
• “Using Dedicated I/O Decoders”
  
  
• “Instantiating LogiBLOX Modules”
  
  
• “Implementing Memory”
  
  
• “Implementing Boundary Scan (JTAG 1149.1)”
  
  
• “Implementing Logic with IOBs”
  
  
• “Implementing Multiplexers with Tristate Buffers”
  
  
• “Using Pipelining”
  
  
• “Design Hierarchy”