Chapter 3

Understanding High-Density Design Flow

This chapter describes the steps in a typical HDL design flow. Although these steps may vary with each design, the information in this chapter is a good starting point for any design. If necessary, refer to the current version of the Quick Start Guide for the Xilinx Alliance Series to familiarize yourself with the Xilinx and interface tools. This chapter includes the following sections.

• “Design Flow”
  
  
• “Entering your Design and Selecting Hierarchy”
  
  
• “Functional Simulation of your Design”
  
  
• “Synthesizing and Optimizing your Design”
  
  
• “Setting Timing Constraints”
  
  
• “Evaluating Design Size and Performance”
  
  
• “Evaluating your Design for Coding Style and System Features”
  
  
• “Placing and Routing Your Design”
  
  
• “Timing Simulation of Your Design”
  
  
• “Downloading to the Device and In-system Debugging”
  
  
• “Creating a PROM File for Stand-Alone Operation”